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參數資料
| 型號： | MTD9N10E |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | TMOS POWER FET 9.0 AMPERES 100 VOLTS RDS(on) = 0.25 OHM |
| 中文描述： | 9 A, 100 V, 0.25 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件頁數： | 1/10頁 |
| 文件大小： | 257K |
| 代理商： | MTD9N10E |
1
Motorola, Inc. 1995
!
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
Replaces MTD6N10
MAXIMUM RATINGS
(TC = 25
°
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
VDGR
VGS
VGSM
100
Vdc
Drain–Gate Voltage (RGS = 1.0 M
)
Gate–Source Voltage — Continuous
Gate–Source Voltage
— Non–Repetitive (tp
≤
10 ms)
100
Vdc
±
20
±
30
Vdc
Vpk
Drain Current — Continuous
Drain Current
— Continuous @ 100
°
C
Drain Current
— Single Pulse (tp
≤
10
μ
s)
ID
ID
IDM
9.0
5.0
27
Adc
Apk
Total Power Dissipation
Derate above 25
°
C
Total Power Dissipation @ TA = 25
°
C, when mounted to minimum recommended pad size
PD
40
0.32
1.75
Watts
W/
°
C
Watts
Operating and Storage Temperature Range
TJ, Tstg
EAS
–55 to 150
°
C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25
°
C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 9.0 Apk, L = 1.0 mH, RG = 25
)
40
mJ
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient, when mounted to minimum recommended pad size
R
θ
JC
R
θ
JA
R
θ
JA
TL
3.13
100
71.4
°
C/W
Maximum Temperature for Soldering Purposes, 1/8
″
from case for 10 seconds
260
°
C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 2
Order this document
by MTD9N10E/D
SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
9.0 AMPERES
100 VOLTS
RDS(on) = 0.25 OHM
Motorola Preferred Device
D
S
G
CASE 369A–13, Style 2
DPAK
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