參數(shù)資料
型號: MTD505
廠商: Electronic Theatre Controls, Inc.
英文描述: 5 Port 10M/100M Ethernet Switch
中文描述: 5端口10M/100M以太網(wǎng)交換機
文件頁數(shù): 4/19頁
文件大?。?/td> 202K
代理商: MTD505
4/19
MTD505 Revision 1.2 14/04/2000
MTD505
(Preliminary)
MYSON
TECHNOLOGY
2.0 PIN DESCRIPTIONS
RMII/MII Port Interface Pins
Name
Pin Number
119
I/O
I
Descriptions
CRSDV0
Port0 RMII receive interface signal, CRSDV0 is asserted high when
port0 media is non_idle.
Port0 RMII receive data bit_0.
Port0 RMII receive data bit_1.
Port0 RMII transmit enable signal.
Port0 RMII transmit data bit_0.
Port0 RMII transmit data bit_1.
Port1 RMII receive interface signal, CRSDV1 is asserted high when
port1 media is non_idle.
Port1 RMII receive data bit_0.
Port1 RMII receive data bit_1.
Port1 RMII transmit enable signal.
Port1 RMII transmit data bit_0.
Port1 RMII transmit data bit_1.
Port2 RMII receive interface signal, CRSDV2 is asserted high when
port2 media is non_idle.
Port2 RMII receive data bit_0.
Port2 RMII receive data bit_1.
Port2 RMII transmit enable signal.
Port2 RMII transmit data bit_0.
Port2 RMII transmit data bit_1.
Port3 RMII receive interface signal, CRSDV0 is asserted high when
port3 media is non_idle.
Port3 RMII receive data bit_0.
Port3 RMII receive data bit_1.
Port3 RMII transmit enable signal.
Port3 RMII transmit data bit_0.
Port3 RMII transmit data bit_1.
Port4 RMII/MII receive interface signal, CRSDV4 is asserted high when
port4 media is non_idle.
Port4 MII receive data valid.
In RMII mode, this pin don’t use.
Port4 MII receive clock signal.
In RMII mode, this pin is not used.
Port4 MII receive data bit_3. In RMII mode, this pin don’t use.
Port4 MII receive data bit_2. In RMII mode, this pin don’t use.
Port4 RMII/MII receive data bit_0.
Port4 RMII/MII receive data bit_1.
Port4 RMII transmit enable signal.
Port4 RMII transmit clock signal.
In RMII mode, this pin is not used.
RXD0_0
RXD0_1
TXEN0
TXD0_0
TXD0_1
CRSDV1
123
124
122
121
120
125
I
I
O
O
O
I
RXD1_0
RXD1_1
TXEN1
TXD1_0
TXD1_1
CRSDV2
01
02
128
127
126
03
I
I
O
O
O
I
RXD2_0
RXD2_1
TXEN2
TXD2_0
TXD2_1
CRSDV3
09
10
06
05
04
11
I
I
O
O
O
I
RXD3_0
RXD3_1
TXEN3
TXD3_0
TXD3_1
CRSDV4
15
16
14
13
12
17
I
I
O
O
O
I
RXDV4
26
I
RXCLK4
25
I
RXD4_3
RXD4_2
RXD4_0
RXD4_1
TXEN4
TXCLK4
32
31
29
30
I
I
I
I
23
24
O
I
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