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參數(shù)資料
| 型號： | MTC20136MB-I1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | ADSL TRANSCEIVER CONTROLLER |
| 中文描述： | 寬帶收發(fā)器控制器 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 634K |
| 代理商： | MTC20136MB-I1 |
MTC20136
16/25
EBI Interface Timing
All timing parameters are specified at a load of 100 pF, all the electrical levels are CMOS compatible.
Table 2. All signals
Table 3. EBI signal timing with respect to E_CLK
CTRLE
The Ctrl-E interface is an ADSL-oriented mailbox system to exchange control and status messages be-
tween MTC20136 and an external controller. It consists of a mailbox and a physical interface. The mailbox
has two 8-bit command registers to pass commands from the MTC20136 internal controller bus (ASB) to
Ctrl-E (RxCommand) and from Ctrl-E to ASB (TxCommand), and two status registers (RxComAv and Tx-
ComAv) to indicate the status of the command register. Data associated with a command can be ex-
changed using a common CtrleDataBuffer. A hardware semaphore mechanism is provided to allow
control of data consistency of the CtrleDataBuffer.
Figure 7. Ctrl-E interface controller principle
Symbol
Parameters
Min
Typ
Max
3
Unit
ns
t
r
,t
f
Ci
Co
Rise and Fall time (10% - 90%)
Input load
Output load
10
100
pF
pF
Symbol
Parameters
Min
3
Max
Unit
ns
T
dh
Data input hold time from E_CLK
T
ds
Data input setup time to E_CLK
10
ns
T
dd
Data/Address output valid/tri-state delay from E_CLK
10
ns
T
wrd
ALE delay from E_CLK
6
ns
T
oed
notOE delay from E_CLK
6
ns
T
wed
notWEi delay from E_CLK (falling edge)
6
ns
T
wrd
W/notR delay from E_CLK
3
10
ns
T
csd
notCSi delay from E_CLK
3
10
ns
Ctrl-E
physical interface
Ctrl-E
Mailbox
CtrleDataBuffer
(512*8 bit
dual port RAM)
Semaphore
RxComAv
TxComAv
RxCommand
TxCommand
Mailbox Interrupt
controller
Ctrl-E
Serial
Interface
Generic
Parallel
Interface
TX
RX
D_SELctrle
I/O
MRd
MWr
MA[8:0]
MD[7:0]
MQ[7:0]
Ctrlelnt1
Ctrlelnt0
ASB
To IT-
Controller
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