參數(shù)資料
型號: MTC20136MB-I1
廠商: 意法半導(dǎo)體
英文描述: ADSL TRANSCEIVER CONTROLLER
中文描述: 寬帶收發(fā)器控制器
文件頁數(shù): 15/25頁
文件大?。?/td> 634K
代理商: MTC20136MB-I1
15/25
MTC20136
Figure 5. SDRAM write access (CAS latency = 3; Burst length = 4)
Memory
Following features are provided for memory access (SRAM or FEPROM) :
– 16 bit databus and 20 bit address bus giving 1Mbyte address space per chip select
– control signals : E_nCS[0:1], E_nOE, E_nWE0, E_nWE1
– setup and wait state insertion
– 8, 16 and 32 bit access by MTC20136 to 8 or 16 bit memory according to little endian convention
Figure 6. EBI memory access (32-bit Word R/W to 16 bit memory), maximum speed timing
EAact
EArw
EApre
S_clk
S_nCS
S_nRAS
S_nCAS
S_nWE
S_DQM[1:0]
S_A[11:0]
S_Q[15:0]
EBI
E_nCSi
E_nOE
E_nWEO
E_nWE1
E_A[19:2]
A1[19:2]
A2[19:2]
E_A[1:0]
00
10
00
10
E_D[15:0]
LSB MSB
MSB
LSB
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