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參數(shù)資料
| 型號： | MT9126 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad ADPCM Transcoder(四ADPCM編解碼器) |
| 中文描述： | 四差分PcM轉碼器（四差分PcM編解碼器） |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 138K |
| 代理商： | MT9126 |
MT9126
8-8
Following the reset (i.e., PWRDN pin brought high)
and assuming that clocks are applied to the MCLK/
C4i and BCLK pins, the internal clocks will still not
begin to operate until the first frame alignment is
detected on the ENB1 pin for SSI mode or on the F0i
pin for ST-BUS mode. The C2o clock and EN1, EN2
pins will not start operation until a valid frame pulse
is applied to the F0i pin. If the F0i pin remains low for
longer than 2 cycles of MCLK/C4i then the C2o pin
will top toggling and will stay low. If the F0i pin is held
high then the C2o pin will continue to operate. In ST-
BUS mode the EN1 and EN2 pins will stop toggling if
the frame pulse (F0i) is not applied every frame.
Master Clock (MCLK/C4i)
A minimum 4096 kHz master clock is required for
execution
of
the
transcoding
algorithm requires 512 cycles of MCLK/C4i during
one frame for proper operation. For SSI operation
this
input,
at
the
MCLK/C4i
asynchronous with the 8 kHz frame provided that the
lowest frequency and deviation due to clock jitter still
meets the strobe period requirement of a minimum of
512 t
C4P
- 25%t
C4P
(see Figure 3). For example, a
system
producing
large
accommodated by running an over-speed MCLK/C4i
that will ensure a minimum 512 MCLK/C4i cycles per
algorithm.
The
pin,
may
be
jitter
values
can
be
frame is obtained. The minimum MCLK/C4i period is
61 ns, which translates to a maximum frequency of
16.384 MHz.
Extra MCLK/C4i cycles (>512/frame)
are acceptable since the transcoder is aligned by the
appropriate strobe signals each frame.
Figure 3 - MCLK/C4i Minimum Requirement
Bit Clock (BCLK)
For SSI operation the bit rate, for both ADPCM and
PCM ports, is determined by the clock input at
BCLK. BCLK must be eight periods in duration and
synchronous with the 8 kHz frame inputs at ENB1
and ENB2. Data is sampled at PCMi1/2 and at
ADPCMi concurrent with the falling edge of BCLK.
Data
is
available
at
PCMo1/2
concurrent with the rising edge of BCLK. BCLK may
be any rate between 128 kHz and 4096 kHz. For ST-
BUS operation BCLK is ignored (tie to V
SS
) and the
bit rate is internally set to 2048 kbit/s.
and
ADPCMo
ENB1
MCLK/C4i
512 t
C4P
- 25%t
C4P
Minimum
Figure 4 - SSI 8-Bit Companded PCM Relative Timing
ADPCM i/o
BCLK
ENB1
ENB2/F0od
PCMi/o1
ADPCM i/o
SEL = 0
SEL = 1
32 kb/s
24 kb/s
16 kb/s
SEL for 16 kb/s only
B1
B2
PCMi/o2
1 2 3 4
B1
B2
1 2 3 x
B1
B2
1 2
B3
B4
1 2 1 2
1 2 1 2 1 2 1 2 1 2
7 6 5
3
4
2 1 0
B3
B4
1 2 3 4
1 2 3 x
1 2 3 4
B3
B4
1 2 3 x
1 2 3 4
1 2 3 x
B1
B2
B3
B4
7 6 5
3
4
2 1 0
7 6 5
3
4
2 1 0 7 6 5
3
4
2 1 0
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT9126AE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Quad ADPCM Transcoder |
| MT9126AE1 | 制造商:Microsemi Corporation 功能描述:ADPCM VOICE COMPRESSION G.726 16KBPS/24KBPS/32KBPS 5V 28PDIP - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TRANSCODER QUAD ADPCM 28PDIP 制造商:Microsemi Corporation 功能描述:IC TRANSCODER QUAD ADPCM 28PDIP |
| MT9126AS | 制造商:Microsemi Corporation 功能描述: |
| MT9126AS1 | 制造商:Microsemi Corporation 功能描述:ADPCM VOICE COMPRESSION G.726 16KBPS/24KBPS/32KBPS 5V 28SOIC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TRANSCODER QUAD ADPCM 28SOIC 制造商:Microsemi Corporation 功能描述:IC TRANSCODER QUAD ADPCM 28SOIC |
| MT9126ASR | 制造商:Microsemi Corporation 功能描述: |
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