
MT9126
8-4
Notes:
All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.
All inputs have TTL compatible logic levels except for MCLK/C4i which has CMOS compatible logic levels and PWRDN which has Schmitt
trigger compatible logic levels.
All outputs are CMOS with CMOS logic levels (See DC Electrical Characteristics).
23
ADPCMi
Serial ADPCM Stream ( Input).
128 kbit/s to 4096 kbit/s serial ADPCM word input
stream. Data bits are clocked in on falling edge of BCLK in SSI mode and clocked in on
the 3/4 bit edge of MCLK/C4i in ST-BUS mode.
24
ADPCMo
Serial ADPCM Stream (Output).
128 kbit/s to 4096 kbit/s serial ADPCM word output
stream. Data bits are clocked out by rising edge of BCLK in SSI mode and clocked out by
MCLK/C4i divided by two in ST-BUS mode.
25
26
27
MS4
MS5
MS6
Mode Selects 4, 5 and 6 (Inputs).
Mode selects for all four decoders.
MS6
MS5
MS4
MODE
0
0
0
32 kbit/s ADPCM
0
0
1
24 kbit/s ADPCM
0
1
0
16 kbit/s ADPCM
in EN1/ENB1 when SEL=0
in EN2/ENB2 when SEL=1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
ADPCM Bypass for 32 kbit/s and 24 kbit/s
ADPCM Bypass for 16 kbit/s
PCM Bypass (64 kbit/s) to PCM1 if SEL=0, PCM2 if SEL=1
Algorithm reset (ITU-T optional reset)
PCMo1/2 disable
28
EN2
Enable Strobe 2 (Output).
This 8 bit wide, active high strobe is active during the B2
PCM channel in ST-BUS mode. Forced to high impedance when LINEAR=1.
Pin Description (continued)
Pin #
Name
Description
Functional Description
The Quad-channel ADPCM Transcoder is a low
power, CMOS device capable of four encode and
four decode operations per frame. Four 64 kbit/s
channels (PCM octets) are compressed into four 32,
24 or 16 kbit/s ADPCM channels (ADPCM words),
and four 32, 24 or 16 kbit/s ADPCM channels
(ADPCM words) are expanded into four 64 kbit/s
PCM
channels
(PCM
transcoding algorithm utilized conforms to ITU-T
recommendation G.726 (excluding 40 kb/s), and
ANSI T1.303 - 1989. Switching on-the-fly between
32 and 24 kbit/s transcoding is possible by toggling
the appropriate mode select pins (supports T1
robbed-bit signalling).
octets).
The
ADPCM
All functions supported by the device are pin
selectable. The four encode functions comprise a
common group controlled via Mode Select pins MS1,
MS2 and MS3. Similarily, the four decode functions
form a second group commonly controlled via Mode
Select pins MS4, MS5 and MS6. All other pin
controls are common to the entire transcoder.
The device requires 25 mWatts (MCLK/C4i= 4.096
MHz) typically for four channel transcode operation.
A minimum master clock frequency of 4.096 MHz is
required for the circuit to complete four encode
channels and four decode channels per frame. For
SSI operation a master clock frequency greater than
4.096 MHz and asynchronous, relative to the 8 kHz
frame, is allowed.
The PCM and ADPCM serial busses support both
ST-BUS and Synchronous Serial Interface (SSI)
operation. This allows serial data clock rates from
128 kHz to 4096 kHz, as well as compatibility with
Mitel’s standard Serial Telecom BUS (ST-BUS). For
ST-BUS operation, on chip channel counters provide
channel enable outputs as well as a 2048 kHz bit
clock output which may be used by down-stream
devices utilizing the SSI bus interface.
Linear coded PCM is also supported. In this mode
the
encoders
compress,
complement
(S,S,S,12,...,1,0),
channels into four 4, 3 or 2 bit ADPCM channels.
Similarly, the decoder expands four 4, 3 or 2 bit
ADPCM channels into four 16-bit, two’s complement
(S,14,...,1,0), uniform PCM channels. The data rate
for both ST-BUS and SSI operation in this mode is
2048 kbit/s.
four
14-bit,
uniform
two’s
PCM