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參數(shù)資料
| 型號(hào)： | MT9126 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad ADPCM Transcoder(四ADPCM編解碼器) |
| 中文描述： | 四差分PcM轉(zhuǎn)碼器（四差分PcM編解碼器） |
| 文件頁(yè)數(shù)： | 6/25頁(yè) |
| 文件大小： | 138K |
| 代理商： | MT9126 |
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MT9126
8-6
16 kbit/s ADPCM Mode
When SEL is set to 0, the 8-bit PCM octets of the B1,
B2, B3 and B4 channels (PCMi1 and PCMi2) are
compressed
into
four
2-bit
ADPCMo during the ENB1 timeslot in SSI mode and
during the B1 timeslot in ST-BUS mode. Similarily,
the four 2-bit ADPCM words on ADPCMi are
expanded into four 8-bit PCM octets (on PCMo1 and
PCMo2) during the ENB1/B1 timeslot. (See Figures 4
& 7.)
ADPCM
words
on
When SEL is set to 1, The same conversion takes
place as described when SEL = 0 except that the
ENB2/B2 timeslots are utilized.
A-Law or
μ
-Law 8-bit PCM are received and
transmitted most significant bit first starting with b7
and
ending
with
b0.
ADPCM
significant bit first starting with I1 and ending with I2.
data
are
most
ADPCM BYPASS (32 and 24 kbit/s)
In ADPCM bypass mode the B1 and B2 channel
ADPCM words are bypassed (with a two-frame
delay) to/from the ADPCM port and placed into the
most significant nibbles of the PCM1/2 port octets.
Note that the SEL pin performs no function for these
two modes (See Figures 6 & 9). LINEAR, FORMAT
and A/
μ
pins are ignored in bypass mode.
In 32 kb/s ADPCM bypass mode, Bits 1 to 4 of the
B1, B2, B3 and B4 channels from PCMi1 and PCMi2
are transparently passed, with a two frame delay, to
the same channels on ADPCMo. In the same
manner, the B1, B2, B3 and B4 channels from
ADPCMi are transparently passed, with a two frame
delay, to the same channels on PCMo1 and PCMo2
pins. Bits 5 to 8 are don’t care. This feature allows
two
voice
terminals,
transcoding, to communicate through a system
without
incurring
unnecessary
conversions. This arrangement allows byte-wide or
nibble-wide transport through a switching matrix.
which
utilize
ADPCM
transcode
24 kb/s ADPCM bypass mode is the same as 32 kb/s
mode bypass excepting that only bits 1 to 3 are
bypassed and bits 4 to 8 are don’t care.
ADPCM BYPASS (16 kbit/s)
When SEL is set to 0, only bits 1 and 2 of the B1, B2,
B3 and B4 PCM octets (on PCMi1 and PCMi2) are
bypassed, with a two frame delay, to the same
channels on ADPCMo during the ENB1 timeslot in
SSI mode and during the B1 timeslot in ST-BUS
mode. Similarily, the four 2-bit ADPCM words on
ADPCMi are transparently bypassed, with a two
frame delay, to PCMo1 and PCMo2 during the ENB1
or B1 timeslot. Bits 3-8 are don’t care. (See Figures 6
& 9.)
When SEL is set to 1, the same bypass occurs as
described when SEL = 0 except that the ENB2 or B2
timeslots are utilized.
LINEAR, FORMAT and A/
μ
pins are ignored in
bypass mode.
PCM BYPASS
When SEL is set to 0, the B1 and B2 PCM channels
on PCMi1 are transparently passed, with a two-
frame delay, to the same channels on the ADPCMo.
Simiarily, the two 8-bit words which are on ADPCMi
are transparently passed, with a two-frame delay, to
channels B1 and B2 of PCMo1 while PCMo2 is set
to a high-impedance state.(See Figures 6 & 9.)
When SEL is set to 1, the B3 and B4 channels on
PCMi2 are transparently passed, with a two frame
delay, to the same channels on ADPCMo. Similarily,
the two 8-bit words which are on ADPCMi are
transparently passed, with a two-frame delay, to
channels B3 and B4 of PCMo2. In this case PCMo1
is always high-impedance if ENB1 = 0. If ENB1 = 1
during ST-BUS operation then the D and C channels
are active on PCMo1.
LINEAR, FORMAT and A/
μ
pins are ignored in
bypass mode.
Algorithm Reset Mode
While an algorithmic reset is asserted the device will
incrementally converge its internal variables to the
'Optional reset values' stated in G.726. Algorithmic
reset requires that the master clock (MCLK/C4i) and
frame pulse (ENB1/2 or F0i) remain active and that
the reset condition be valid for at least four frames.
Note that this is not a power down mode; see
PWRDN for this function.
ADPCMo & PCMo1/2 Disable
When the encoders are programmed for ADPCMo
disable (MS1 to MS3 set to 1) the ADPCMo output is
set to a high impedance state and the internal
encode
function
remains
convergence is maintained. The decode processing
function and data I/O remain active.
active.
Therefore
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9126AE | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Quad ADPCM Transcoder |
| MT9126AE1 | 制造商:Microsemi Corporation 功能描述:ADPCM VOICE COMPRESSION G.726 16KBPS/24KBPS/32KBPS 5V 28PDIP - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TRANSCODER QUAD ADPCM 28PDIP 制造商:Microsemi Corporation 功能描述:IC TRANSCODER QUAD ADPCM 28PDIP |
| MT9126AS | 制造商:Microsemi Corporation 功能描述: |
| MT9126AS1 | 制造商:Microsemi Corporation 功能描述:ADPCM VOICE COMPRESSION G.726 16KBPS/24KBPS/32KBPS 5V 28SOIC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TRANSCODER QUAD ADPCM 28SOIC 制造商:Microsemi Corporation 功能描述:IC TRANSCODER QUAD ADPCM 28SOIC |
| MT9126ASR | 制造商:Microsemi Corporation 功能描述: |
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