- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384760 > MT90863AL1 (Mitel Networks Corporation) 3V Rate Conversion Digital Switch PDF資料下載
參數(shù)資料
| 型號： | MT90863AL1 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 3V Rate Conversion Digital Switch |
| 中文描述： | 3V的速率轉(zhuǎn)換數(shù)字開關(guān) |
| 文件頁數(shù)： | 24/35頁 |
| 文件大小： | 154K |
| 代理商： | MT90863AL1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
MT90863
Advance Information
24
JTAG Support
The MT90863 JTAG interface conforms to the
Boundary-Scan IEEE1149.1 standard. This stan-
dard specifies a design-for-testability technique
called Boundary-Scan Test (BST). The operation of
the boundary-scan circuitry is controlled by an
external Test Access Port (TAP) Controller.
Test Access Port (TAP)
The Test Access Port (TAP) accesses the MT90863
test functions. It consists of three input pins and one
output pin as follows:
Test Clock Input (TCK)
TCK provides the clock for the test logic.
The TCK does not interfere with any on-chip
clock and thus remains independent. The
TCK permits shifting of test data into or out
of
the
Boundary-Scan
concurrently with the operation of the device
and without interfering with the on-chip
logic.
register
cells
Test Mode Select Input (TMS)
The TAP Controller uses the logic signals
received at the TMS input to control test
operations. The TMS signals are sampled at
the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven
from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed
either into the instruction register or into a
test data register, depending on the
sequence previously applied to the TMS
input. Both registers are described in a
subsequent section. The received input data
is sampled at the rising edge of TCK pulses.
This pin is internally pulled to Vdd when it is
not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously
applied to the TMS input, the contents of
either the instruction register or data
register are serially shifted out towards the
TDO. The data out of the TDO is clocked on
the falling edge of the TCK pulses. When no
data is shifted through the boundary scan
cells, the TDO driver is set to a high
impedance state.
Test Reset (TRST
)
Reset the JTAG scan structure. This pin is
internally pulled to VDD.
Instruction Register
The MT90863 uses the public instructions defined in
the IEEE 1149.1 standard. The JTAG Interface
contains a two-bit instruction register. Instructions
are serially loaded into the instruction register from
the TDI when the TAP Controller is in its shifted-IR
state. These instructions are subsequently de-coded
to achieve two basic functions: to select the test data
register that may operate while the instruction is
current; and, to define the serial test data register
path that is used to shift data between TDI and DO
during data register scan-ning.
Test Data Register
As specified in IEEE 1149.1, the MT90863 JTAG
Interface contains three test data registers:
The Boundary-Scan Registe
r
The Boundary-Scan register consists of a
series of Boundary-Scan cells arranged to
form a scan path around the boundary of
the MT90863 core logic.
The Bypass Register
The Bypass register is a single stage shift
register that provides a one-bit path from
TDI to its TDO.
The Device Identification Register
The device identification register is a 32-bit
register. The register contents are:
The LSB bit in the device identification register is
the first bit clock out.
The MT90863 scan register contains 212 bits. Bit 0
in Table 23 Boundary Scan Register is the first bit
clocked out. All tri-state enable bits are active high.
MSB
LSB
0000 0000 1000 0110 0011 0001 0100 1011
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90863 | 3V Rate Conversion Digital Switch(3V 速率轉(zhuǎn)換數(shù)字開關(guān)) |
| MT9125 | Dual ADPCM Transcoder(雙ADPCM編解碼器) |
| MT91600 | Programmable SLIC(可編程用戶線路接口電路（在轉(zhuǎn)換系統(tǒng)和用戶環(huán)間提供一個接口）) |
| MT9162 | 5 Volt Single Rail Codec(5V 單軌編解碼器) |
| MT9174 | ISO2-CMOS ST-BUS⑩ FAMILY Digital Network Interface Circuit with Receive Sync Marker Bit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90866 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| MT90866AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2.375K X 2.375K/4K X 2.375K/2K X 2K 16.384GBPS 3 - Trays 制造商:Microsemi Corporation 功能描述:FLEXIBLE DIGITAL SWITCH WITH H.110 INTER 制造商:Microsemi 功能描述:SWIT FABRIC 2.375K X 2.375K/4K X 2.375K/2K X 2K 16.384GBPS 3 |
| MT90866AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2.375K X 2.375K/4K X 2.375K/2K X 2K 16.384GBPS 3 - Trays 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE DIG SWITCH+ H.110 INTER |
| MT90866AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:WAN Access Switch |
| MT90868AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。