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參數(shù)資料
| 型號： | MT90863AL1 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | 3V Rate Conversion Digital Switch |
| 中文描述： | 3V的速率轉換數(shù)字開關 |
| 文件頁數(shù)： | 11/35頁 |
| 文件大?。?/td> | 154K |
| 代理商： | MT90863AL1 |
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Advance Information
MT90863
11
Figure 7 - Block Programming Data in the Connection Memories
A7
(Note 1)
A6
A5
A4
A3
A2
A1
A0
Location
0
0
0
0
0
0
0
0
Control Register, CR
0
0
0
0
0
0
0
1
Device Mode Selection Register, DMS
0
0
0
0
0
0
1
0
Internal Mode Selection Register, IMS
0
0
0
0
0
0
1
1
Frame Alignment Register, FAR
0
0
0
0
0
1
0
0
Input Offset Selection Register 0, DOS0
0
0
0
0
0
1
0
1
Input Offset Selection Register 1, DOS1
0
0
0
0
0
1
1
0
Input Offset Selection Register 2, DOS2
0
0
0
0
0
1
1
1
Input Offset Selection Register 3, DOS3
0
0
0
0
1
0
0
0
Input Offset Selection Register 4, DOS4
0
0
0
0
1
0
0
1
Input Offset Selection Register 5, DOS5
0
0
0
0
1
0
1
0
Frame Output Offset Register, FOR0
0
0
0
0
1
0
1
1
Frame Output Offset Register, FOR1
0
0
0
0
1
1
0
0
Address Buffer Register, ABR
0
0
0
0
1
1
0
1
Data Write Register, DWR
0
0
0
0
1
1
1
0
Data Read Register, DRR
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 0
Ch 1
.
Ch 30
Ch 31
(
Note 2)
1
1
.
1
1
0
0
.
1
1
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 32
Ch 33
.
Ch 126
Ch 127
(
Note 3)
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2Mb/s.
3. Channels 0 to 127 are used when serial stream is at 8Mb/s
Table 4 - Address Memory Map
7
6
5
4
3
2
1
0
8
9
10
11
12
13
0
BBPD
0
BBPD
1
BBPD
2
14
15
0
0
0
0
0
0
0
0
0
0
0
0
Backplane Connection Memory (BCM)
7
6
5
4
3
2
1
0
8
9
10
11
12
13
0
LBPD
0
LBPD
1
14
15
0
LBPD
2
0
0
0
0
0
0
0
0
0
0
3
Local Connection Memory Low (LCML)
7
6
5
4
3
2
1
0
8
9
10
11
12
13
0
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Local Connection Memory High (LCMH)
0
LBPD
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