參數(shù)資料
型號: MT90863AL1
廠商: Mitel Networks Corporation
英文描述: 3V Rate Conversion Digital Switch
中文描述: 3V的速率轉(zhuǎn)換數(shù)字開關(guān)
文件頁數(shù): 17/35頁
文件大?。?/td> 154K
代理商: MT90863AL1
Advance Information
MT90863
17
Table 10 - Frame Delay Offset (DOS) Register Bits
Name
(Note 1)
Description
IFn2, IFn1, IFn0
Input Offset Bits 2,1 & 0.
These three bits define how long the serial interface receiver
takes to recognize and store bit 0 from the STio pin: i.e., to start a new frame. The input
frame offset can be selected to +4 clock periods from the point where the external frame
pulse input signal is applied to the F0i inputs of the device.
DLEn
Data Latch Edge.
ST-BUS mode:
DLEn =0, if clock rising edge is at the 3/4 point of the bit cell.
DLEn =1, if clock falling edge is at the 3/4 point of the bit cell.
Note 1: n denotes a STio stream number from 0 to 23.
Read/Write Address:
04
H
for DOS0 register,
05
H
for DOS1 register,
06
H
for DOS2 register,
07
H
for DOS3 register,
08
H
for DOS4 register,
09
H
for DOS5 register,
0000
H
for all DOS registers.
Reset value:
7
6
5
4
3
2
1
0
8
9
10
11
12
13
DLE0
IF00
IF01
IF02
14
15
DLE1
IF10
IF11
IF12
DLE2
IF20
IF21
IF22
DLE3
IF30
IF31
IF32
DOS0 register
DOS1 register
7
6
5
4
3
2
1
0
8
9
10
11
12
13
DLE4
IF40
IF41
IF42
14
15
DLE5
IF50
IF51
IF52
DLE6
IF60
IF61
IF62
DLE7
IF70
IF71
IF72
DOS2 register
7
6
5
4
3
2
1
0
8
9
10
11
12
13
DLE8
IF80
IF81
IF82
14
15
DLE9
IF90
IF91
IF92
DLE10
IF100
IF101
IF102
DLE11
IF110
IF111
IF112
DOS3 register
7
6
5
4
3
2
1
0
8
9
10
11
12
13
DLE12
IF120
IF121
IF122
14
15
DLE13
IF130
IF131
IF132
DLE14
IF140
IF141
IF142
DLE15
IF150
IF151
IF152
DOS4 register
7
6
5
4
3
2
1
0
8
9
10
11
12
13
DLE16
IF160
IF161
IF162
14
15
DLE17
IF170
IF171
IF172
DLE18
IF180
IF181
IF182
DLE19
IF190
IF191
IF192
DOS5 register
7
6
5
4
3
2
1
0
8
9
10
11
12
13
DLE20
IF200
IF201
IF202
14
15
DLE21
IF210
IF211
IF212
DLE22
IF220
IF221
IF222
DLE23
IF230
IF231
IF232
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