
MT90863
Advance Information
4
92
B13
C4i/C8i
HMVIP/CT Bus Clock (5V Tolerant Input):
When HMVIP mode is
enabled, this pin accepts a 4.096MHz clock for HMVIP frame pulse
alignment. When CT Bus mode is enabled, it accepts a 8.192MHz
clock for CT frame pulse alignment.
94
A13
F0o
Frame Pulse (5V Tolerant Output):
A 244ns wide negative frame
pulse that is phase locked to the master frame pulse (F0i).
95
C12
C4o
C4 Clock (5V Tolerant Output):
A 4.096MHz clock that is phase
locked to the master clock (C16i).
98-105,
108-115
C11, B12, B11,
A12, A11, B10,
A10, B9, A9,
C8, B8, A8, C7,
B7, A7, A6,
STio0 - 15
FEi0 - 15
Serial Input Streams 0 to 15 / Frame Evaluation Inputs 0 to 15 (5V
Tolerant I/O).
In 2Mb/s and HMVIP modes, these pins accept serial
TDM data streams at 2.048 Mb/s with 32 channels per stream. In 4Mb/
s or 8Mb/s mode, these pins accept serial TDM data streams at 4.096
or 8.192 Mb/s with 64 or 128 channels per stream respectively. In
Frame Evaluation Mode (FEM), they are frame evaluation inputs.
118-125
B6, A5, B5, A4,
B4, C4, A3, B3
STio16 - 23
FEi16 - 23
Serial Input Streams 16 to 23 (5V Tolerant I/O).
In 2Mb/s or 4Mb/s
mode, these pins accept serial TDM data streams at 2.048 or 4.096
Mb/s with 32 or 64 channels per stream respectively. In HMVIP mode,
these pins have a data rate of 8.192Mb/s with 128 channels per
stream. In Frame Evaluation Mode (FEM), they are frame evaluation
inputs.
128,
1-7
A2, B2, A1, C3,
C2, B1, D3, D2
STio24 - 31
Serial Input Streams 24 to 31 (5V Tolerant I/O).
These pins are only
used for 2Mb/s or 4Mb/s mode. They accept serial TDM data streams
at 2.048 or 4.096 Mb/s with 32 or 64 channels per stream respectively.
9
C1
TMS
Test Mode Select (3.3V Input with internal pull-up):
JTAG signal
that controls the state transitions of the TAP controller.
10
D1
TDI
Test Serial Data In (3.3V Input with internal pull-up):
JTAG serial
test instructions and data are shifted in on this pin.
11
E2
TDO
Test Serial Data Out (3.3V Output):
JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in a high impedance
state when JTAG scan is not enabled.
12
E1
TCK
Test Clock (5V Tolerant Input):
Provides the clock to the JTAG test
logic.
13
F2
TRST
Test Reset (3.3 V Input with internal pull-up):
Asynchronously
initializes the JTAG TAP controller by putting it in the Test-Logic-Reset
state. This pin should be pulsed low on power-up, or held low
continuously, to ensure that the MT90863 is in the normal operation
mode.
14
F3
IC1
Internal Connection 1 (3.3V Input with internal pull-down):
Connect to V
SS
for normal operation.
Device Reset (5V Tolerant Input):
This input (active LOW) puts the
MT90863 in its reset state. This clears the device’s internal counters
and registers.
15
F1
RESET
16
G3
IC2
Internal Connection 2 (3.3V Input):
Connect to V
SS
for normal operation.
Address 0 - 7 (5V Tolerant Input):
These lines provide the A0 to A7
address lines to the internal memories.
18-25
G1, H1, H2, H3,
J2, J1,J3, K1
A0 - A7
Pin Description (continued)
128 MQFP
Pin#
144 BGA
Pin#
Name
Description