參數(shù)資料
型號(hào): MT90863
廠商: Mitel Networks Corporation
英文描述: 3V Rate Conversion Digital Switch(3V 速率轉(zhuǎn)換數(shù)字開(kāi)關(guān))
中文描述: 3V的速率轉(zhuǎn)換數(shù)字交換機(jī)(3V的速率轉(zhuǎn)換數(shù)字開(kāi)關(guān))
文件頁(yè)數(shù): 16/35頁(yè)
文件大小: 168K
代理商: MT90863
MT90863
Advance Information
16
Table 9 - Frame Alignment (FAR) Register Bit
Figure 8 - Example for Frame Alignment Measurement
Bit
Name
Description
15-11
FE4-0
Frame Evaluation Input Select.
The binary value expressed in these bits refers
to the frame evaluation inputs, FEi0 to FEi23.
10
CFE
Complete Frame Evaluation.
When CFE = 1, the frame evaluation is completed
and bits FD9 to FD0 bits contains a valid frame alignment offset. This bit is reset to
zero, when SFE bit in the IMS register is changed from 1 to 0. This bit is read-only.
9
FD9
Frame Delay Bit 11.
The falling edge of FE is sampled during the CLK-high
phase (FD9 = 1) or during the CLK-low phase (FD9 = 0). This bit allows the
measurement resolution to 1/2 CLK cycle. This bit is read-only.
8-0
FD8-0
Frame Delay Bits.
The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of the
IMS register changes from 1 to 0. (FD8 = MSB, FD0 = LSB). These bits are also
read-only
Read/Write Address:
Reset Value:
03
H
,
0000
H
.
7
6
5
4
3
2
1
0
8
9
10
11
12
13
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
FD8
FD9
CFE
FE0
FE1
FE2
FE3
FE4
14
15
ST-BUS F0i
FEi Input
(FD9 = 0, sample at CLK low phase)
Offset Value
(FD[8:0] = 06
H
)
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C16i
HMVIP F0i
FEi Input
(FD9 = 1, sample at CLK high phase)
Offset Value
(FD[8:0] = 08
H
)
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C16i
C4i
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