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參數(shù)資料
| 型號： | MT9085B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | PAC - Parallel Access Circuit(并行存取電路) |
| 中文描述： | 委員會-并行訪問電路（并行存取電路） |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 111K |
| 代理商： | MT9085B |
MT9085B
2-133
Serial to Parallel Conversion
The MT9085 can be configured to perform serial to
parallel conversion by tying the MCA pin low. A
single PAC will accept 1024 channels on the 32 or 16
serial streams and output the data onto the parallel
bus as illustrated in Figure 8.
The data on the serial input streams can be clocked
in at 2.048 Mbit/s or at 4.096 Mbit/s by setting the
appropriate level on the 2/4S pin. See Figures 16
and 17 for timing details.
Data is clocked out on the parallel bus with the C16
clock (see Figure 18 for timing details). The parallel
output bus will be actively driven for two C16 clock
periods when MCB is tied high. Data is output with
every second rising clock edge. Setting MCB low will
enable the output drivers for only one C16 clock
period in any specific parallel channel timeslot. The
actual phase relationship between the system frame
boundary and the parallel output timeslots is affected
by the level asserted on the CKD input (see Figure
7). The flexibility in output timing permits the PAC to
be easily interfaced to the SMX in 1024 and 2048
channel configurations. Refer to the applications
section of this data sheet for more information.
The delay through the PAC is approximately one
ST-BUS channel when the device is configured for
2.048 Mbit/s serial rate. In the 4.096 Mbit/s mode,
the delay is equal to approximately eight C4 clock
cycles.
Timing and Framing Signals
The PAC requires two clock signals. A 16.384 MHz
master clock (C16) is used to clock data in and out of
the device on the parallel bus. A 4.096 MHz clock
(C4i), phase locked to C16i, clocks in the frame
pulse. The positive C16i edge immediately after the
C4i falling edge which clocks in F0i defines the
internal frame boundary. The two separate clock
inputs permit synchronization of the MT9085 to
system timing in which the frame pulse is derived
from a 4.096 MHz clock.
The PAC generates all framing signals necessary to
construct a 1024 channel or a 2048 channel switch
matrix using the SMX. The DFPo signal is used as a
framing signal for the SMXs operated as the Data
Memory. The CFPo is used to synchronize Connect
Memory timing in a typical 1K or 2K switch
application (refer to the application section in this
data sheet for more information). The timing of both
DFPo and CFPo signals is affected by the level
asserted on the CKD input as shown in Figure 15.
The PAC outputs ST-BUS timing signals, F0o, C2o
and C4o derived from C16i. The phase relationship
between the frame boundary established by F0i and
F0o is illustrated in Figures 4 and 5.
Applications
1024 Channel Digital Time-Space Switch
A 1024 channel serial time-space digital switch
design is illustrated in Figure 9.
The main switching function is accomplished using
two MT9080s (SMXs). One SMX is operated in the
Data Memory mode and the second serves as the
Connection Memory. Refer to the SMX data sheet for
more information on this configuration. The serial to
parallel conversion function is provided by a PAC
configured for 2.048 Mbit/s operation (2/4S = 0). The
MCB input in this PAC is tied high to ensure data
output by the PAC meets SMX input setup and hold
requirement. PAC #2 performs the parallel to serial
function; MCA is set high. The MCB input in this
device is set low to allow data to be clocked in with
the falling edge of C16.
The main timing source generates a 16.384MHz
clock phase locked to a 4.096MHz clock. The
framing signal input to PAC#1 at F0i should meet the
requirements specified in Figure 13 of this data
sheet. In some applications where a master 16.384
MHz oscillator is used for system timing, the C4i and
F0i clocks could be derived directly from it. In
applications where a 4.096 MHz clock signal is
available, the 16.384 MHz clock can be generated
using a phase-lock loop.
Framing signals for both the SMXs are generated by
PAC #1. DFPo is connected to FP input of the Data
Memory. CFPo is connected to the FP input of the
Connection Memory. PAC #2 is configured to
perform parallel to serial conversion.
The DFPo and CFPo signals ensure that all timing
requirements necessary to interface the SMXs with
the PACs are met while input and output serial
frames are aligned.
The maximum delay through the switch is
approximately one frame plus two serial channels
when SMX#1 is operated in Data Memory Mode-1.
When the SMX is operated in Data Memory Mode-2,
the maximum delay is two frames. In this case, the
channels are double buffered; frame integrity is
maintained for all switching configurations.
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