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參數(shù)資料
| 型號： | MT9085B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | PAC - Parallel Access Circuit(并行存取電路) |
| 中文描述： | 委員會-并行訪問電路（并行存取電路） |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 111K |
| 代理商： | MT9085B |
MT9085B
2-128
Pin #
Name
Description
48
DFPo
Data Memory Frame Pulse (Output).
Framing signal with nominal 4 kHz frequency; changes
state 64 (CKD=0) or 65 (CKD=1) C16 clock cycles after the frame boundary established by F0i.
This signal is a complement of DFPo. See Figure 15 for timing information. The signal is used
by SMXs (MT9080s) making up the Data Memory in a typical 1k or 2k switch configuration.
49
F0o
Framing Type 0 Signal (Output).
8 kHz framing signal output by the PAC to indicate the frame
boundary synchronized to C16. This framing signal is aligned with C4o and is output by the
PAC for use by other devices in a typical switch configuration. Refer to Figures 4 and 5 for
functional timing information.
50
F0i
Framing Type 0 Signal (TTL compatible input).
This input signal establishes the frame
boundary for the serial input/output streams. The first falling edge of C4i following the falling
edge of F0i establishes the frame boundaries. Refer to Figure 13 for timing information.
51
C16i
16 MHz Clock Input.
The 16.384 MHz clock signal input at this pin must be phase-locked to
the 4.096 MHz clock input at C4i. See Figure 13 for timing information.
52
V
SS
V
DD
DFPo
Ground.
53
Supply Input. +5V.
54
Data Memory Frame Pulse (Output).
4 kHz framing signal; changes state 64 (CKD=0) or 65
(CKD=1) C16 clock cycles after the frame boundary established by F0i. This signal is a
complement of DFPo. See Figure 15. The signal is used by SMXs (MT9080s) making up the
Data Memory in a typical 2k switch configuration.
55
C4o
4.096 MHz Clock Output.
This is a 4.096 MHz clock signal derived from the 16 MHz master
clock input at C16. The falling edge of C4o occurs in the middle of the regenerated frame pulse
output at F0o. Refer to Figures 4 and 5 for functional timing information.
56
C2o
2.048 MHz Clock Output.
This is a 2.048 MHz clock signal derived from the 16 MHz master
clock input. The rising edge of this clock signal occurs in the middle of the regenerated frame
pulse output at F0o. Refer to Figures 4 and 5 for functional timing information.
57
NC
No Connection.
58
V
SS
MCB
Ground.
59
Mode Control-B (Input).
This control input performs two different functions, depending on the
state of MCA pin.
In parallel to serial mode (MCA=1), MCB defines which clock edge latches in the data.
MCB=0
Data on the parallel bus is latched into the device with the every second falling
edge of C16. See Figure 6.
MCB=1
Data on the parallel bus is latched into the device with every alternate positive
clock edge.
In serial to parallel mode (MCA=0), the MCB pin controls the state of the parallel bus driver as
follows:
MCB=0
The output drivers are enabled for only half the timeslot. The data is clocked out
on the first falling edge within the timeslot and disabled on the next falling edge.
See Figure 7.
MCB=1
The parallel data bus output drivers are enabled for the duration of the channel
timeslot (two C16 Clock Periods). The data is clocked out on the first positive
edge within a timeslot and disabled on the last edge.
60-67
P0-P7
Parallel Input/Output Data Bus.
This 8 bit data bus is an output in serial to parallel mode
(MCA=0), and an input in parallel to serial mode (MCA=1). Data is clocked in and out of the
port by the C16 clock. The state of the CKD pin determines the relative phase of the critical
clock edges with respect to the frame pulse. All inputs/outputs have internal pullups. Refer to
Figures 6 and 7 for functional timing information.
68
V
DD
Supply.
+5V.
Pin Description (continued)
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