參數(shù)資料
型號(hào)： MT9085B
廠(chǎng)商： Mitel Networks Corporation
英文描述： PAC - Parallel Access Circuit(并行存取電路)
中文描述： 委員會(huì)-并行訪(fǎng)問(wèn)電路（并行存取電路）
文件頁(yè)數(shù)： 14/21頁(yè)
文件大小： 111K
代理商： MT9085B
MT9085B
2-138
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 13 - ST-BUS Frame Pulse and Clock Timing
Timing is over recommended temperature & power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 14 - F0o, C4o and C2o Output Clock Timing
AC Electrical Characteristics
- Input Frame Pulse and Clock Timing (See Figure 13)
-
Voltages are with respect to Ground (V
SS
) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
C16 Clock Period
t
C16P
t
C4P
t
C16L
t
C16H
t
C4S
t
FPS
t
FPH
60
61
62
ns
2
C4 Clock Period
219
244
269
ns
3
C16 Pulse Width Low
25
ns
4
C16 Pulse Width High
25
ns
5
C4 Setup Time
-10
25
ns
6
Frame Pulse Setup Time
5
200
ns
7
Frame Pulse Hold Time
5
ns
AC Electrical Characteristics
- Output Clocks and Frame Pulse Timing (See Figure 14) -
Voltages are with respect to Ground (V
SS
) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Frame Pulse Delay
t
FPD
t
C4D
t
C2D
0
31
ns
C
L
=85pF
C
L
=85pF
C
L
=85pF
2
C4 Clock Delay
0
28
ns
3
C2 Clock Delay
0
ns
t
C16P
t
C16H
t
C16L
t
C4S
t
C4P
t
FPS
t
FPH
C16i
C4i
F0i
ST-BUS Frame Boundary
C16i
F0o
C4o
C2o
t
FPD
t
C4D
t
C4D
t
C2D
t
FPD
t
C4D
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