參數(shù)資料
型號: MT90826
廠商: Mitel Networks Corporation
英文描述: Quad Digital Switch(四數(shù)字開關(guān))
中文描述: 四數(shù)字交換機(四數(shù)字開關(guān))
文件頁數(shù): 6/30頁
文件大小: 131K
代理商: MT90826
MT90826
6
Serial Interface Mode
Input Stream
Input Data Rate
Output Stream
Output Data Rate
8 Mb/s
STi0-31
8 Mb/s
STo0-31
8 Mb/s
16 Mb/s
STi0-15
16 Mb/s
STo0-15
16 Mb/s
4 Mb/s and 8 Mb/s
STi0-15
4 Mbs/
STo0-15
4 Mb/s
STi15-31
8 Mb/s
STo16-31
8 Mb/s
16 Mb/s and 8 Mb/s
STi0-11
16 Mb/s
STo0-11
16 Mb/s
STi12-19
8 Mb/s
STo12-19
8 Mb/s
4 Mb/s
STi0-31
4 Mb/s
STo0-31
4 Mb/s
2 Mb/s and 4 Mb/s
STi0-15
2 Mb/s
STo0-15
2 Mb/s
STi16-31
4 Mb/s
STo16-31
4 Mb/s
2 Mb/s
STi0-31
2 Mb/s
STo0-31
2 Mb/s
Table 1 - Stream Usage under Various Operation Modes
Device Overview
The MT90826 Quad Digital Switch is capable of
switching up to 4,096
×
4,096 channels. The
MT90826 is designed to switch 64 kbit/s PCM or N x
64k bit/s data. The device maintains frame integrity
in data applications and minimum throughput delay
for voice applications on a per channel basis.
The serial input streams of the MT90826 can have a
bit rate of 2.048, 4.096, 8.192 or 16.384 Mbit/s and
are arranged in 125
μ
s wide frames, which contain
32, 64,128 or 256 channels, respectively. The data
rates on input and output streams match. All inputs
and outputs may be programmed to 2.048, 4.096 or
8.192 Mb/s. STi0-15 and STo0-15 may be set to
16.384 Mb/s. Combinations of two bit rates, N and
2N are provided. See Table 1.
By using Mitel’s message mode capability, the
microprocessor can access input and output
timeslots on a per channel basis. This feature is
useful for transferring control and status information
for external circuits or other ST-BUS devices.
To correct for backplane delays, the MT90826 has a
frame offset calibration function which allows uses to
measure the frame delay on any of the input
streams, This information can then be used to
program the input offset dealy for each individual
stream. Refer to Table 7, 8, and 9 and Figure 4 and
5. In addition, the Mt90826 allow users to advance
the output data position upto 45ns to compensate for
the output delay caused by excessive output loading
conditions.
The microport interface is compatible with Motorola
non-multiplexed
buses.
locations may be directly written to or read from; data
memory locations may be directly read from. A DTA
signal is provided to hold the bus until the
asynchronous microport operation is queued into the
device.
Connection
memory
Functional Description
A functional Block Diagram of the MT90826 is shown
in Figure 1.
Data and Connection Memory
For all data rates, the received serial data is
converted to parallel format by internal serial-to-
parallel converters and stored sequentially in the
data memory. Depending upon the selected
operation programmed in the control register, the
usable data memory may be as large as 4,096 bytes.
The sequential addressing of the data memory is
performed by an internal counter, which is reset by
the input 8 kHz frame pulse (F0i) to mark the frame
boundaries of the incoming serial data streams.
Data to be output on the serial streams may come
from either the data memory or connection memory.
Locations in the connection memory are associated
with particular ST-BUS output channels. When a
channel is due to be transmitted on an ST-BUS
output, the data for this channel can be switched
either from an ST-BUS input in connection mode, or
from the lower half of the connection memory in
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