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參數(shù)資料
| 型號： | MT90826 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad Digital Switch(四數(shù)字開關(guān)) |
| 中文描述： | 四數(shù)字交換機（四數(shù)字開關(guān)） |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 131K |
| 代理商： | MT90826 |
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MT90826
13
Table 7 - Frame Alignment (FAR) Register Bits
DR2
DR1
DR0
Serial Interface Mode
CLK
(CPLL=0)
CLK
(CPLL=1)
0
0
0
8 Mb/s
16.384MHz
16.384MHz
0
0
1
16 Mb/s
0
1
0
4 and 8 Mb/s
0
1
1
16 and 8 Mb/s
1
0
0
4 Mb/s
16.384MHz
8.192MHz
1
0
1
2 and 4 Mb/s
1
1
0
2 Mb/s
16.384MHz
8.192MHz
Table 6 - Serial Data Rate Selections and External Clock Rates
Bit
Name
Description
15-11
FE4-0
Frame Evaluation Input Select.
The binary value expressed in these bits
refers to the frame evaluation inputs, FEi0 to FEi31.
10
CFE
Complete Frame Evaluation.
When CFE = 1, the frame evaluation is
completed and FD9 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the control register is changed from 1
to 0.
9
FD9
Frame Delay Bit 9.
The falling edge of FEi input is sampled during the internal
master clock high phase (FD9 = 1) or during the low phase (FD9 = 0). This bit
allows the measurement resolution to 1/2 internal master clock cycle.
See Figure 4 for clock signal alignment.
Internal Master Clock
C8i 2Mb/s
C16i 4Mb/s, 2&4Mb/s
C32i 8Mb/s, 16Mb/s, 4&8Mb/s, 16&8Mb/s
Operation Mode
8-0
FD8-0
Frame Delay Bits.
The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the control register changes from 1 to 0. (FD8 = MSB, FD0 = LSB)
Read/Write Address:
Reset Value:
0001
H
,
0000
H
.
7
6
5
4
3
2
1
0
8
9
10
11
12
13
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
FD8
FD9
CFE
FE0
FE1
FE2
FE3
FE4
14
15
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