參數(shù)資料
型號(hào)： MT90826
廠商： Mitel Networks Corporation
英文描述： Quad Digital Switch(四數(shù)字開(kāi)關(guān))
中文描述： 四數(shù)字交換機(jī)（四數(shù)字開(kāi)關(guān)）
文件頁(yè)數(shù)： 4/30頁(yè)
文件大?。?/td> 131K
代理商： MT90826
MT90826
4
34
N11
TMS
Test Mode Select (3.3V Input with Internal pull-up).
JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up
when not driven.
35
M11
TDI
Test Serial Data In (3.3V Input with Internal pull-up).
JTAG serial test instructions and data are shifted in on this
pin. This pin is pulled high by an internal pull-up when not
driven.
36
N12
TDO
Test Serial Data Out (3.3V Output).
JTAG serial data is
output on this pin on the falling edge of TCK. This pin is
held in high impedance state when JTAG scan is not
enabled.
37
N13
TCK
Test Clock (5V Tolerant Input).
Provides the clock to the
JTAG test logic.
38
M12
TRST
Test Reset (3.3V Input with internal pull-up).
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be
pulsed low on power-up, or held low, to ensure that the
device is in the normal functional mode.
42
L11
IC1
Internal Connection 1 (3.3V Input with internal pull-
down).
Connect to V
SS
for normal operation.
Device Reset (5V Tolerant Input).
This input (active
LOW) puts the device in its reset state which clears the
device internal counters and registers.
43
M13
RESET
44
L12
IC2
Internal Connection 2 (3.3V Input with internal pull-
down).
Connect to V
SS
for normal operation.
Internal Connection 3 (3.3V Input with internal pull-
down).
Connect to V
SS
for normal operation.
Master Frame Pulse (5V Tolerant Input).
This input
accepts a 60ns wide negative frame pulse.
46
L13
IC3
47
K12
F0i
50
K10
PLLGND
Phase Lock Loop Ground.
51
K9
PLLVDD
Phase Lock Loop Power Supply. 3.3V
52
K13
CLK
Master Clock (5V Tolerant Input).
Serial clock for shifting
data in/out on the serial streams. This pin accepts a clock
frequency of 8.192MHz or 16.384 MHz. The CPLL bit in
the control register determines the usage of the clock
frequency. See Table 6 for details.
55
J13
ODE
Output Drive Enable (5V Tolerant Input).
This is the
output-enable control pin for the STo0 to STo31 serial
outputs. See Table 2 for details.
Pin Description (continued)
Pin # MQFP
Pin # PBGA
Name
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90826AG 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays
MT90826AG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays
MT90826AL 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160MQFP - Trays
MT90826AL1 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160MQFP - Trays 制造商:Microsemi Corporation 功能描述:PB FREE QUAD DIGITAL SWITCH
MT90826AV 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 144LBGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH QDX QUAD 144LBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH QDX QUAD 144LBGA
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