參數(shù)資料
型號： MT9076AB
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 3.3V Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器
文件頁數(shù)： 135/160頁
文件大?。?/td> 416K
代理商： MT9076AB
Preliminary Information
MT9076
131
Bit
Name
Functional Description
7
INTSEL
Interrupt Selection.
When high, this bit will cause bit 2 of the Interrupt Register to reflect
a TX FIFO underrun (TXunder). When low, this interrupt will reflect a frame abort (FA).
6
CYCLE
Cycle.
When high, this bit will cause the transmit byte count to reload one minus the
value initially loaded into the Transmit Byte Count Register.
5
TxCRCI
Transmit CRC Inhibited.
When high, this bit will inhibit transmission of the CRC. That is,
the transmitter will not insert the computed CRC onto the bit stream after seeing the EOP
tag byte. This is used in V.120 terminal adaptation for synchronous protocol sensitive UI
frames.
4
SEVEN
Seven Bit Address Recognition.
When high, this bit will enable seven bits of address
recognition in the first address byte. The received address byte must have bit 0 equal to 1
which indicates a single address byte is being received.
3
- -
Reserved
, must be zero for normal operation.
2
- -
Reserved
, must be zero for normal operation.
1
RxFRST
RX FIFO Reset.
When high, the RX FIFO will be reset. This causes the receiver to be
disabled until the next reception of a flag. The status register will identify the FIFO as
being empty. However, the actual bit values in the RX FIFO will not be reset.
0
TxFRST
TX FIFO Reset.
When high, the TX FIFO will be reset. The Status Register will identify
the FIFO as being empty. This bit will be reset when data is written to the TX FIFO.
However, the actual bit values of data in the TX FIFO will not be reset. It is cleared by the
next write to the TX FIFO.
Table 163 - HDLC Control Register 2
(Page B,C & D, Address 15H)
Bit
Name
Functional Description
7-0
GaIM
RxEOPIM
TxEOPIM
RxFEIM
TxFLIM
FA:TxUNDE
RIMRxFFIM
RxOVFIM
This register is used with the Interrupt Register to mask out the interrupts that are not
required by the microprocessor. Interrupts that are masked out will not drive the pin
IRQ low; however, they will set the appropriate bit in the Interrupt Register. An
interrupt is disabled when the microprocessor writes a 0 to a bit in this register.
This register is cleared on power reset.
Table 164 - HDLC Interrupt Mask Register
(Page B,C & D, Address 16H)
相關(guān)PDF資料
PDF描述
MT9076 T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9076AP 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver
MT9076B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver
MT9076BB 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays
MT9076BB1 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays
MT9076BP 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver
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