參數(shù)資料
型號： MT9076AB
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 3.3V Single Chip Transceiver
中文描述： T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器
文件頁數(shù)： 106/160頁
文件大小： 416K
代理商： MT9076AB
MT9076
Preliminary Information
102
Table 102 - LIU Receive Word (E1)
(Page 1, Address 1FH)
Bit
Name
Functional Description
7
HDLC0IM
HDLC0 Interrupt Mask
. When unmasked an interrupt is triggered by an unmasked event in
HDLC0. If 1 - unmasked, 0 - masked.
6
HDLC1IM
HDLC1 Interrupt Mask
. When unmasked an interrupt is triggered by an unmasked event in
HDLC1. If 1 - unmasked, 0 - masked.
5
HDLC2IM
HDLC2 Interrupt Mask
. When unmasked an interrupt is triggered by an unmasked event in
HDLC2. If 1 - unmasked, 0 - masked.
4
JAIM
Jitter Attenuation Interrupt Mask.
When unmasked, an interrupt will be initiated when the
jitter attenuator FIFO comes within four bytes of an overflow or underflow condition. If 1 -
unmasked, 0 - masked.
3
1SECIM
One Second Status Interrupt Mask
. When unmasked (1SECI = 1), an interrupt is initiated
when the 1SEC status bit changes from zero to one. If 1- unmasked, 0 - masked.
2
5SECIM
Five Second Status Interrupt Mask
. When unmasked (5SECI = 1), an interrupt is initiated
when the 5SECI status bit changes from zero to one. If 1- unmasked, 0 - masked.
1
RCRIM
RCRI Interrupt Mask.
Whenever an unmasked (RCRI=1), an interrupt is initiated when RCR
(remote alarm & CRC-4 error) status bit changes from zero to one. If 1- unmasked, 0 - masked.
0
SIGIM
signaling (CAS) Interrupt Mask
. When unmasked and any of the receive ABCD bits of any
channel changes state an interrupt is initiated. If 1 - unmasked, 0 - masked..
Table 101 - Interrupt Mask Word Three (E1)
(Page 1, Address 1EH)
Bit
Name
Functional Description
7
NRZ
NRZ Format Selection
. Only used in the digital framer only mode (LIU is
disabled). A one sets the MT9076 to accept a unipolar NRZ format input
stream on RxA as the line input, and to transmit a unipolar NRZ format
stream on TxB. A zero causes the MT9076 to accept a complementary pair
of dual rail inputs on RxA/RxA and to transmit a complementary pair of dual
rail outputs on TxA/TxB.
6 - 4
- - -
Reserved
. Set this bit low for normal operation.
3-2
RxA1-0
Automatic Receive Equalizer Control
. If either bit is the receive equalizer is
turned on and will compensate for loop length automatically. The control bits
RxEQ2-0 will be ignored. The combinations 11, 10 and 01 decode three
different equalization algorithms. If both are set low (00) then equalization will
be actived using the control bits RxEQ2-0.
2-0
RxEQ2-0
Receive Equalization Select
. Setting these pins forces a level of
equalization of the incoming line data.
RES2 RES1 RES0 Receive Equalization
0 0 0 none
0 0 1 8 dB
0 1 0 16 dB
0 1 1 24 dB
1 0 0 32 dB
1 0 1 40 dB
1 1 0 48 dB
1 1 1 reserved
These settings have no effect if either of RxA1 and RxA0 are set to one.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9076AP 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver
MT9076B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver
MT9076BB 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays
MT9076BB1 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays
MT9076BP 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver
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