參數(shù)資料
型號: MT9075B
廠商: Mitel Networks Corporation
英文描述: E1 Single Chip Transceiver(E1單片收發(fā)器)
中文描述: 素E1單芯片收發(fā)器(素E1單片收發(fā)器)
文件頁數(shù): 34/82頁
文件大?。?/td> 275K
代理商: MT9075B
MT9075B
Preliminary Information
34
Table 20 - National Use Bit Interrupt Mask Word
(Page 01H, Address 19H)
Table 21 - Interrupt, Signalling and BERT
Control Word (Page 01H, Address 1AH)
(continued)
Bit
Name
Functional Description
7
---
Unused.
6
PRBSO
(0)
PRBS
Interrupt.
(PRBSO = 1), an interrupt is
initiated on overflow of PRBS
counter (page 04H, address 10H)
from FFH to 0H. Interrupt vector =
00000010.
Counter
When
Overflow
unmasked
5
PRBSI
(0)
PRBS Interrupt.
When unmasked
(PRBSI = 1), an interrupt is initiated
on a single PRBS detection error.
Interrupt vector = 00000010.
4
S
a
nibI
(0)
Changed S
a
Nibble Interrupt.
When unmasked (S
a
nibI = 1), an
interrupt
is
generated
detection of a change of state in any
of received S
a
nibbles (nibble S
a5
,
nibble S
a6
, nibble S
a7
or nibble S
a8
).
Interrupt vector = 00000010.
upon
3
S
a
bitI
(0)
Changed S
a
Bit Interrupt.
When
unmasked (S
a
bitI = 1), an interrupt
is generated upon detection of a
change of state in any of received
S
a
bits (S
a5
, S
a6
, S
a7
or S
a8
).
Interrupt vector = 00000010.
2
C8S
a6
I
(0)
Eight Consecutive S
a6
Nibble
Interrupt.
When unmasked (C8S
a6
I
= 1), an interrupt is generated upon
detection of the eighth consecutive
S
a6
nibble with the same pattern.
Interrupt vector = 00000010.
1
S
a6
I
(0)
Changed S
a6
Nibble Interrupt.
When unmasked (S
a6
I = 1), an
interrupt
is
generated
detection of a change of state in
received S
a6
nibbles. Interrupt
vector = 00000010.
upon
0
S
a5
I
(0)
Changed S
a5
Bit Interrupt.
When
unmasked (S
a5
I =1), an interrupt is
generated upon detection of a
change of state in the received S
a5
bit. Interrupt vector = 00000010.
Bit
Name
Functional Description
7
ODE
(0)
Output Data Enable.
If one, the
DSTo and CSTo output drivers
function normally. When low, DSTo
and CSTo will be tristated.
Note:
When ODE =1, DSTo and
CSTo can be individually tristated
by DSToDE and CSToDE (page
01H, address 16H) respectively.
6
SPND
(0)
Suspend Interrupts.
If one, the
IRQ output (pin 12 in PLCC, 85 in
MQFP) will be in a high-impedance
state and all interrupts will be
ignored. If zero, the IRQ output will
function normally.
5
INTA
(0)
Interrupt Acknowledge.
A zero-to-
one or one-to-zero transition will
clear any pending interrupt and
make IRQ high.
4
TxCCS
(0)
Transmit
Signalling.
If one, the transmit
section of the device is in common
channel signalling (CCS) mode. If
zero, it is in Channel Associated
Signalling (CAS) mode.
Common
Channel
3
RPSIG
(0)
Register
Signalling.
If one, the transmit CAS
signalling will be controlled by
programming page 05H. If zero, the
transmit CAS signalling will be
controlled through the CSTi stream.
Programmed
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