參數(shù)資料
型號： MT9044
廠商： Mitel Networks Corporation
英文描述： T1/E1/OC3 System Synchronizer(T1/E1/OC3 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）)
中文描述： T1/E1/OC3系統(tǒng)同步器（T1/E1/OC3系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成））
文件頁數(shù)： 4/34頁
文件大?。?/td> 150K
代理商： MT9044
MT9044
4
34
28
LOS1
Primary Reference Loss (TTL Input).
Typically, external equipment applies a
logic high to this input when the PRI reference signal is lost or invalid. The logic
level at this input is gated in by the rising edge of F8o. See LOS2 description. This
pin is internally pulled down to VSS.
35
29
TDO
Test Serial Data Out (TTL Output).
JTAG serial data is output on this pin on the
falling edge of TCK. This pin is held in high impedance state when JTAG scan is
not enabled.
36
30
MS2
Mode/Control Select 2 (TTL Input).
This input, in conjunction with MS1,
determines the device’s mode (Automatic or Manual) and state (Normal, Holdover
or Freerun) of operation. The logic level at this input is gated in by the rising edge
of F8o. See Table 3.
37
31
MS1
Mode/Control Select 1 (TTL Input).
rising edge of F8o. See pin description for MS2. This pin is internally pulled down
to VSS.
The logic level at this input is gated in by the
38
32
RSEL
Reference Source Select (TTL Input).
In Manual Control, a logic low selects the
PRI (primary) reference source as the input reference signal and a logic high
selects the SEC (secondary) input. In Automatic Control, this pin must be at logic
low. The logic level at this input is gated in by the rising edge of F8o. See Table 2.
This pin is internally pulled down to VSS.
39
33
IC
Internal Connection.
Tie low for normal operation.
40
34
FS2
Frequency Select 2 (TTL Input).
This input, in conjunction with FS1, selects
which of three possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input
to the PRI and SEC inputs. See Table 1.
41
35
FS1
Frequency Select 1 (TTL Input).
See pin description for FS2.
42
36
TDI
Test Serial Data In (TTL Input).
JTAG serial test instructions and data are shifted
in on this pin. This pin is internally pulled up to V
DD
.
Reset (Schmitt Input).
A logic low at this input resets the MT9044. To ensure
proper operation, the device must be reset after changes to the method of control,
reference signal frequency changes and power-up. The RST pin should be held
low for a minimum of 300ns. While the RST pin is low, all frame and clock outputs
are at logic high. Following a reset, the input reference source and output clocks
and frame pulses are phase aligned as shown in Figure 19.
43
37
RST
44
38
TMS
Test Mode Select (TTL Input).
JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
DD
.
Pin Description (continued)
Pin #
PLCC
Pin #
MQFP
Name
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9044AL 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 5V 44MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/OC3/T1 5V 44MQFP - Trays
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MT9044AP 制造商:Microsemi Corporation 功能描述:
MT9044AP1 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 5V 44PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:T1/E1/OC3 SYSTEM SYNCHRONIZER 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER T1/E1 44PLCC 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER T1/E1 44PLCC
MT9044APR1 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 5V 44PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/OC3/T1 5V 44PLCC - Tape and Reel
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