參數(shù)資料
型號(hào): MT58L512L18PS-7.5IT
元件分類: SRAM
英文描述: 512K X 18 CACHE SRAM, 4 ns, PQFP100
封裝: PLASTIC, MS-026BHA, TQFP-100
文件頁(yè)數(shù): 9/32頁(yè)
文件大?。?/td> 616K
代理商: MT58L512L18PS-7.5IT
17
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L512L18P_2.p65 – Rev. 6/01
2001, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X00
X...X11
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
FUNCTION
GW#
BWE#
BWa#
BWb#
READ
H
X
READ
H
L
H
WRITE Byte “a”
HL
LH
WRITE Byte “b”
HLHL
WRITE All Bytes
H
L
WRITE All Bytes
L
X
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)
FUNCTION
GW#
BWE#
BWa#
BWb#
BWc#
BWd#
READ
H
X
READ
H
L
H
WRITE Byte “a”
HL
LH
H
WRITE All Bytes
H
LLLL
L
WRITE All Bytes
L
XXXX
X
NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MT58L512V18P 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 PIPELINED, SCD SYNCBURST SRAM