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參數(shù)資料
| 型號： | MT58L32L36PT-7.5 |
| 元件分類： | SRAM |
| 英文描述： | 32K X 36 CACHE SRAM, 4.2 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 354K |
| 代理商： | MT58L32L36PT-7.5 |
16
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L64L18P_B.p65 – Rev. B, Pub. 11/02
2002, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
READ/WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
BWE#,
BWa#-BWd#
(NOTE 4)
Q
High-Z
ADV#
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
D
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWH
tWS
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
(NOTE 1)
tKQLZ
tKQ
Back-to-Back
WRITEs
A1
(NOTE 5)
DON’T CARE
UNDEFINED
A3
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
tADSS
1.7
2.0
2.2
ns
tWS
1.7
2.0
2.2
ns
tDS
1.7
2.0
2.2
ns
tCES
1.7
2.0
2.2
ns
tAH
0.5
ns
tADSH
0.5
ns
tWH
0.5
ns
tDH
0.5
ns
tCEH
0.5
ns
READ/WRITE TIMING PARAMETERS
-6
-7.5
-10
SYMBOL MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tKC
6.0
7.5
10
ns
fKF
166
133
100
MHz
tKH
1.7
1.9
3.2
ns
tKL
1.7
1.9
3.2
ns
tKQ
3.5
4.2
5.0
ns
tKQLZ
1.5
ns
tOELZ
0
ns
tOEHZ
3.5
4.2
4.5
ns
tAS
1.7
2.0
2.2
ns
-6
-7.5
-10
SYMBOL MIN
MAX
MIN
MAX
MIN
MAX
UNITS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L512L18D | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM |
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