參數(shù)資料
型號(hào)： MT58L32L36PT-7.5
元件分類： SRAM
英文描述： 32K X 36 CACHE SRAM, 4.2 ns, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 7/18頁(yè)
文件大?。?/td> 354K
代理商： MT58L32L36PT-7.5
15
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L64L18P_B.p65 – Rev. B, Pub. 11/02
2002, Micron Technology, Inc.
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWE#,
BWa#-BWd#
Q
High-Z
ADV#
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
D
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADSH
tADSS
tADSH
tADSS
tOEHZ
tAAH
tAAS
tWH
tWS
tDH
tDS
(NOTE 3)
(NOTE 1)
(NOTE 4)
GW#
tWH
tWS
(NOTE 5)
Byte write signals are
ignored for first cycle when
ADSP# initiates burst.
ADSC# extends burst.
ADV# suspends burst.
DON’T CARE
UNDEFINED
NOTE: 1. D(A2) refers to input for address A2. Q(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH.
When CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents
input/output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device;
or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
WRITE TIMING PARAMETERS
-6
-7.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tKC
6.0
7.5
10
ns
fKF
166
133
100
MHz
tKH
1.7
1.9
3.2
ns
tKL
1.7
1.9
3.2
ns
tOEHZ
3.5
4.2
4.5
ns
tAS
1.7
2.0
2.2
ns
tADSS
1.7
2.0
2.2
ns
tAAS
1.7
2.0
2.2
ns
tWS
1.7
2.0
2.2
ns
-6
-7.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tDS
1.7
2.0
2.2
ns
tCES
1.7
2.0
2.2
ns
tAH
0.5
ns
tADSH
0.5
ns
tAAH
0.5
ns
tWH
0.5
ns
tDH
0.5
ns
tCEH
0.5
ns
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