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參數(shù)資料
| 型號： | MT58L32L36P |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 32K x 36, 3.3V I/O, Pipelined, SCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| 中文描述： | 32K的× 36，3.3V的I / O的流水線，SCD的SyncBurst的SRAM（1兆，3.3V的輸入/輸出，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器） |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 329K |
| 代理商： | MT58L32L36P |
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, SCD SyncBurst SRAM
MT58L64L18P.p65 – Rev. 9/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
15
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, SCD SYNCBURST SRAM
WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWE#,
BWa#-BWd#
Q
High-Z
ADV#
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
D
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADSH
tADSS
tADSH
tADSS
tOEHZ
tAAH
tAAS
tWH
tWS
tDH
tDS
(NOTE 3)
(NOTE 1)
(NOTE 4)
GW#
tWH
tWS
(NOTE 5)
Byte write signals are
ignored for first cycle when
ADSP# initiates burst.
ADSC# extends burst.
ADV# suspends burst.
DON’T CARE
UNDEFINED
NOTE:
1. D(A2) refers to input for address A2. Q(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH.
When CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents
input/output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18
device; or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
WRITE TIMING PARAMETERS
-6
-7.5
-10
SYM
t
KC
f
KF
t
KH
t
KL
t
OEHZ
t
AS
t
ADSS
t
AAS
t
WS
MIN
6.0
MAX
MIN
7.5
MAX
MIN
10
MAX
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
166
133
100
1.7
1.7
1.9
1.9
3.2
3.2
3.5
4.2
4.5
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
2.2
2.2
2.2
2.2
-6
-7.5
-10
SYM
t
DS
t
CES
t
AH
t
ADSH
t
AAH
t
WH
t
DH
t
CEH
MIN
1.7
1.7
0.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
2.2
2.2
0.5
0.5
0.5
0.5
0.5
0.5
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
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