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參數(shù)資料
| 型號： | MT55L64L36F1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 64K x 36,3.3V I/O, ZBT SRAM(2Mb,3.3V輸入/輸出，靜態(tài)RAM) |
| 中文描述： | 64K的x 36,3.3六/ O的ZBT SRAM的（處理器，3.3V的輸入/輸出，靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 15/23頁 |
| 文件大?。?/td> | 406K |
| 代理商： | MT55L64L36F1 |
15
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM
MT55L128L18F1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, FLOW-THROUGH ZBT SRAM
I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS
(0
°
C
≤
T
A
≤
+70
°
C; V
DD
, V
DD
Q = +3.3V ±0.165V unless otherwise noted)
DESCRIPTION
Power Supply
Current:
Operating
Power Supply
Current: Idle
CONDITIONS
SYMBOL
TYP
-10
-12
UNITS NOTES
Device selected; All inputs
≤
V
IL
or
≥
V
IH
;
Cycle time
≥
t
KC (MIN);
V
DD
= MAX; Outputs open
Device selected; V
DD
= MAX;
CKE#
≥
V
IH
;
All inputs
≤
V
SS
+ 0.2 or
≥
V
DD
- 0.2;
Cycle time
≥
t
KC (MIN)
Device deselected; V
DD
= MAX;
All inputs
≤
V
SS
+ 0.2 or
≥
V
DD
- 0.2;
All inputs static; CLK frequency = 0
Device deselected; V
DD
= MAX;
All inputs
≤
V
IL
or
≥
V
IH
;
All inputs static; CLK frequency = 0
Device deselected; V
DD
= MAX;
All inputs
≤
V
SS
+ 0.2 or
≥
V
DD
- 0.2;
Cycle time
≥
t
KC (MIN)
ZZ
≥
V
IH
I
DD
85
225
185
mA
1, 2, 3
I
DD
1
5
12
10
mA
1, 2, 3
CMOS Standby
I
SB
2
0.5
10
10
mA
2, 3
TTL Standby
I
SB
3
7
25
25
mA
2, 3
Clock Running
I
SB
4
25
65
60
mA
2, 3
Snooze Mode
I
SB
2
Z
0.5
10
10
mA
3
MAX
NOTE:
1. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times and
greater output loading.
2.
“
Device deselected
”
means device is in a deselected cycle as defined in the truth table.
“
Device selected
”
means device
is active (not in deselected mode).
3. Typical values are measured at 3.3V, 25
°
C, and 12ns cycle time.
4. This parameter is sampled.
5. Preliminary package data.
TQFP THERMAL RESISTANCE
DESCRIPTION
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Top of Case)
CONDITIONS
SYMBOL
θ
JA
TYP
40
UNITS NOTES
°
C/W
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
4
θ
JC
8
°
C/W
4
FBGA THERMAL RESISTANCE
DESCRIPTION
Junction to Ambient
(Airflow of 1m/s)
CONDITIONS
SYMBOL
θ
JA
TYP
40
UNITS NOTES
°
C/W
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
4, 5
Junction to Case (Top)
Junction to Pins
(Bottom)
θ
JC
θ
JB
9
°
C/W
°
C/W
4, 5
4, 5
17
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