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參數(shù)資料
| 型號： | MT55L512V18PF-6 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 3.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, FBGA-165 |
| 文件頁數(shù)： | 9/25頁 |
| 文件大小： | 304K |
| 代理商： | MT55L512V18PF-6 |
17
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18P_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
NOTE: 1. VDDQ = +3.3V ±0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O
configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
3. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device
is active (not in deselected mode).
4. Typical values are measured at +3.3V, +25°C and 10ns cycle time.
5. This parameter is sampled.
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0°C
≤ T
A ≤ +70°C; VDD = +3.3V ±0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-6
-7.5
-10
UNITS NOTES
Power Supply
Device selected; All inputs
≤ VIL
Current: Operating
or
≥ VIH; Cycle time ≥ tKC (MIN);
IDD
200
500
400
300
m A
2, 3, 4
VDD = MAX; Outputs open
Power Supply
Device selected; VDD = MAX;
Current: Idle
CKE#
≥ VIH;IDD1
10
25
20
m A
2, 3, 4
All inputs
≤ VSS + 0.2 or ≥ VDD - 0.2;
Cycle time
≥ tKC (MIN)
CMOS Standby
Device deselected; VDD = MAX;
All inputs
≤ VSS + 0.2 or ≥ VDD - 0.2;
ISB2
0.5
10
m A
3, 4
All inputs static; CLK frequency = 0
TTL Standby
Device deselected; VDD = MAX;
All inputs
≤ VIL or ≥ VIH;ISB3
6
252525
m A
3, 4
All inputs static; CLK frequency = 0
Clock Running
Device deselected; VDD = MAX;
ADV/LD#
≥ VIH; All inputs ≤ VSS + 0.2
ISB4
45
120
75
60
m A
3, 4
or
≥ VDD - 0.2; Cycle time ≥ tKC (MIN)
Snooze Mode
ZZ
≥ VIH
ISB2Z
0.5
10
m A
4
MAX
TQFP THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Thermal Resistance
Test conditions follow standard test methods
θ
JA
40
°C/W
5
(Junction to Ambient)
and procedures for measuring thermal
Thermal Resistance
impedance, per EIA/JESD51.
θ
JC
8
°C/W
5
(Junction to Top of Case)
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