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參數(shù)資料
| 型號： | MT55L512V18PF-6 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 3.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, FBGA-165 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 304K |
| 代理商： | MT55L512V18PF-6 |
22
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18P_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
NOP, STALL, AND DESELECT CYCLES
READ
Q(A3)
456
789
10
CLK
CE#
R/W#
CKE#
BWx#
ADV/LD#
ADDRESS
A3
A4
A5
D(A4)
DQ
COMMAND
A1
Q(A5)
WRITE
D(A4)
STALL
WRITE
D(A1)
123
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
tKHQZ
tKHQX
A2
D(A1)
Q(A2)
Q(A3)
NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not
performed during this cycle.
2. For this waveform, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
NOP, STALL, AND DESELECT TIMING PARAMETERS
-6
-7.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tKHQX
1.5
ns
tKHQZ
1.5
3.5
1.5
3.5
1.5
3.5
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L512Y32PF-10 | 制造商:Micron Technology Inc 功能描述: |
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| MT55L512Y36FT10 | 制造商:Micron Technology Inc 功能描述: |
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