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參數(shù)資料
| 型號： | MT55L512V18PF-6 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 3.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, FBGA-165 |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 304K |
| 代理商： | MT55L512V18PF-6 |
18
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18P_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
NOTE: 1. This parameter is sampled.
2. OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for
turnaround timing.
3. Test conditions as specified with output loading as shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V ±0.165V) and
Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V).
4. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
5. Measured as HIGH above VIH and LOW below VIL.
6. Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion on these parameters.
7. This parameter is sampled.
8. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
9. Transition is measured ±200mV from steady state voltage.
10. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times
with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK when ADV/LD# is LOW to remain enabled.
11. Preliminary package data.
AC ELECTRICAL CHARACTERISTICS
(Notes 2, 3, 4) (0°C
≤ T
A ≤ +70°C; VDD = +3.3V ±0.165V unless otherwise noted)
-6
-7.5
-10
DESCRIPTION
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
Clock
Clock cycle time
tKHKH
6.0
7.5
10
ns
Clock frequency
fKF
166
133
100
MHz
Clock HIGH time
tKHKL
1.7
2.0
3.2
ns
5
Clock LOW time
tKLKH
1.7
2.0
3.2
ns
5
Output Times
Clock to output valid
tKHQV
3.5
4.2
5.0
ns
Clock to output invalid
tKHQX
1.5
ns
6
Clock to output in Low-Z
tKHQX1
1.5
ns
6, 7, 8, 9
Clock to output in High-Z
tKHQZ
1.5
3.5
1.5
3.5
1.5
3.5
ns
6, 7, 8, 9
OE# to output valid
tGLQV
3.5
4.2
5.0
ns
2
OE# to output in Low-Z
tGLQX
0
ns
6, 7, 8, 9
OE# to output in High-Z
tGHQZ
3.5
4.2
5.0
ns
6, 7, 8, 9
Setup Times
Address
tAVKH
1.5
1.7
2.0
ns
10
Clock enable (CKE#)
tEVKH
1.5
1.7
2.0
ns
10
Control signals
tCVKH
1.5
1.7
2.0
ns
10
Data-in
tDVKH
1.5
1.7
2.0
ns
10
Hold Times
Address
tKHAX
0.5
ns
10
Clock enable (CKE#)
tKHEX
0.5
ns
10
Control signals
tKHCX
0.5
ns
10
Data-in
tKHDX
0.5
ns
10
FBGA THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Junction to Ambient
Test conditions follow standard test methods
θ
JA
40
°C/W
1, 11
(Airflow of 1m/s)
and procedures for measuring thermal
Junction to Case (Top)
impedance, per EIA/JESD51.
θ
JC
9
°C/W
1, 11
Junction to Pins (Bottom)
θ
JB
17
°C/W
1, 11
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