參數(shù)資料
型號(hào)： MT55L256L32FT-12
元件分類(lèi)： SRAM
英文描述： 256K X 32 ZBT SRAM, 9 ns, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 22/25頁(yè)
文件大?。?/td> 300K
代理商： MT55L256L32FT-12
6
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18F_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
TQFP PIN DESCRIPTIONS
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
37
SA0
Input
Synchronous Address Inputs: These inputs are registered
36
SA1
and must meet the setup and hold times around the rising
32-35, 44-50,
S A
edge of CLK. Pin 84 is reserved as an address bit for the
80-83, 99,
81-83, 99,
higher-density 18Mb ZBT SRAM. SA0 and SA1 are the two
100
least significant bits (LSB) of the address field and set the
internal burst counter if burst is desired.
93
BWa#
Input
Synchronous Byte Write Enables: These active LOW
94
BWb#
inputs allow individual bytes to be written when a WRITE
–
95
BWc#
cycle is active and must meet the setup and hold times
–
96
BWd#
around the rising edge of CLK. BYTE WRITEs need to be
asserted on the same cycle as the address. BWa# controls
DQa pins; BWb# controls DQb pins; BWc# controls DQc
pins; BWd# controls DQd pins.
89
CLK
Input
Clock: This signal registers the address, data, chip enables,
byte write enables and burst control inputs on its rising
edge. All synchronous inputs must meet setup and hold
times around the clock’s rising edge.
98
CE#
Input
Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# is LOW).
92
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# is LOW). This
input can be used for memory depth expansion.
97
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# is LOW). This
input can be used for memory depth expansion.
86
OE#
Input
Output Enable: This active LOW, asynchronous input
(G#)
enables the data I/O output drivers. G# is the JEDEC-
standard term for OE#.
85
ADV/LD# Input
Synchronous Address Advance/Load: When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is
loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW
on ADV/LD# clocks a new address at the CLK rising edge.
87
CKE#
Input
Synchronous Clock Enable: This active LOW input permits
CLK to propagate throughout the device. When CKE is
HIGH, the device ignores the CLK input and effectively
internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
64
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When ZZ is
active, all other inputs are ignored.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT55L256L32FT-12IT 制造商:Rochester Electronics LLC 功能描述:- Bulk
MT55L256L32P 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:8Mb ZBT SRAM
MT55L256L32PF-10 制造商:Micron Technology Inc 功能描述:
MT55L256L32PT10 制造商:MICRON 功能描述:*
MT55L256L32PT-10 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 8M-Bit 256K x 32 5ns 100-Pin TQFP 制造商:Micron Technology Inc 功能描述:
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