參數(shù)資料
型號(hào)： MT55L256L32FT-12
元件分類(lèi)： SRAM
英文描述： 256K X 32 ZBT SRAM, 9 ns, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 19/25頁(yè)
文件大?。?/td> 300K
代理商： MT55L256L32FT-12
3
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18F_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
GENERAL DESCRIPTION (continued)
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc#, and BWd#), and
read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK), and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW, or left
unconnected if burst is unused. The flow-through data-
out (Q) is enabled by OE#. WRITE cycles can be from
one to four bytes wide as controlled by the write control
inputs.
All READ, WRITE, and DESELECT cycles are initi-
ated by the ADV/LD# input. Subsequent burst ad-
dresses can be internally generated as controlled by the
burst advance pin (ADV/LD#). Use of burst mode is
optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the flow-through ZBT SRAM uses a LATE WRITE
cycle. For example, if a WRITE cycle begins in clock cycle
one, the address is present on rising edge one. BYTE
WRITEs need to be asserted on the same cycle as the
address. The write data associated with the address is
required one cycle later, or on the rising edge of clock
cycle two.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During a BYTE WRITE cycle, BWa# controls
DQa pins; BWb# controls DQb pins; BWc# controls
DQc pins; and BWd# controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e.,
when ADV/LD# is LOW. Parity/ECC bits are available
only on the x18 and x36 versions.
Micron’s 8Mb ZBT SRAMs operate from a +3.3V VDD
power supply, and all inputs and outputs are LVTTL-
compatible. Users can choose either a 3.3V or 2.5V I/O
version. The device is ideally suited for systems requir-
ing high bandwidth and zero bus turnaround delays.
Please
refer
to
the
Micron
Web
site
(www.micron.com/sramds) for the latest data sheet.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT55L256L32FT-12IT 制造商:Rochester Electronics LLC 功能描述:- Bulk
MT55L256L32P 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb ZBT SRAM
MT55L256L32PF-10 制造商:Micron Technology Inc 功能描述:
MT55L256L32PT10 制造商:MICRON 功能描述:*
MT55L256L32PT-10 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 8M-Bit 256K x 32 5ns 100-Pin TQFP 制造商:Micron Technology Inc 功能描述:
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