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參數(shù)資料
| 型號： | MT4C4256L |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 256K x 4 DRAM Standard Or Low Power, Extended Refresh(標(biāo)準(zhǔn)或低功率，擴(kuò)展刷新，256K x 4動(dòng)態(tài)RAM) |
| 中文描述： | 256K × 4的DRAM標(biāo)準(zhǔn)或低功耗，延長刷新（標(biāo)準(zhǔn)或低功率，擴(kuò)展刷新，256K × 4動(dòng)態(tài)內(nèi)存） |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 240K |
| 代理商： | MT4C4256L |
MT4C4256(L)
REV. 4/94
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
1994, Micron Semiconductor, Inc.
6
MT4C4256(L)
256K x 4 DRAM
OBSOLETE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vcc = +5V
±
10%)
AC CHARACTERISTICS
PARAMETER
Output buffer turn-off delay
Output disable
W
/
E command setup time
Write command hold time
Write command hold time
(referenced to
/
R
A
/
S)
Write command pulse width
Write command to
/
R
A
/
S lead time
Write command to
/
C
A
/
S lead time
Data-in setup time
Data-in hold time
Data-in hold time
(referenced to
/
R
A
/
S)
/
R
A
/
S to
W
/
E delay time
Column-address
to
W
/
E delay time
/
C
A
/
S to
W
/
E delay time
Transition time (rise or fall)
Refresh period (512 cycles)
MT4C4256 / MT4C4256 L
/
R
A
/
S to
/
C
A
/
S precharge time
/
C
A
/
S setup time (CBR REFRESH)
/
C
A
/
S hold time (CBR REFRESH)
O
/
E hold time from
W
/
E during
READ-MODIFY-WRITE cycle
O
/
E setup prior to
/
R
A
/
S during
HIDDEN REFRESH cycle
-6
-7
-8
SYM
t
OFF
t
OD
t
WCS
t
WCH
t
WCR
MIN
3
MAX
20
15
MIN
3
MAX
20
20
MIN
3
MAX
20
20
UNITS
ns
ns
ns
ns
ns
NOTES
20, 26, 28
26
21
0
10
45
0
0
15
55
15
60
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
DHR
10
20
20
0
15
45
15
20
20
0
15
55
15
20
20
0
15
60
ns
ns
ns
ns
ns
ns
22
22
t
RWD
t
AWD
85
60
100
65
110
70
ns
ns
21
21
t
CWD
t
T
40
3
50
3
55
3
ns
ns
21
50
50
50
9, 10
t
REF
t
RPC
t
CSR
t
CHR
t
OEH
8 / 64
8 / 64
8 / 64
ms
ns
ns
ns
ns
0
10
10
15
0
0
10
15
20
10
15
20
5
5
25
t
ORD
0
0
0
ns
24
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