參數(shù)資料
型號(hào): MT4C4256L
廠商: Micron Technology, Inc.
英文描述: 256K x 4 DRAM Standard Or Low Power, Extended Refresh(標(biāo)準(zhǔn)或低功率,擴(kuò)展刷新,256K x 4動(dòng)態(tài)RAM)
中文描述: 256K × 4的DRAM標(biāo)準(zhǔn)或低功耗,延長刷新(標(biāo)準(zhǔn)或低功率,擴(kuò)展刷新,256K × 4動(dòng)態(tài)內(nèi)存)
文件頁數(shù): 2/15頁
文件大小: 240K
代理商: MT4C4256L
MT4C4256(L)
REV. 4/94
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
1994, Micron Semiconductor, Inc.
2
MT4C4256(L)
256K x 4 DRAM
OBSOLETE
in by
/
C
A
/
S.
/
C
A
/
S may be toggled-in by holding
/
R
A
/
S LOW
and strobing-in different column-addresses, thus execut-
ing faster memory cycles. Returning
/
R
A
/
S HIGH terminates
the FAST PAGE MODE cycle.
Returning
/
R
A
/
S and
/
C
A
/
S HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during the
/
R
A
/
S HIGH time. Memory cell data is retained in its correct
state by maintaining power and executing any
/
R
A
/
S cycle
(READ, WRITE) or
/
R
A
/
S REFRESH cycle (
/
R
A
/
S ONLY, CBR,
or HIDDEN) so that all 512 combinations of
R
A
/
S addresses
(A0-A8) are executed at least every 8ms for the MT4C4256
and every 64ms for the MT4C4256 L, regardless of sequence.
The CBR REFRESH cycle will invoke the internal refresh
counter for automatic
/
R
A
/
S addressing.
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
A0
A1
A2
A3
A4
A5
A6
A7
A8
RAS
9
9
9
NO. 2 CLOCK
GENERATOR
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR
Vcc
Vss
9
REFRESH
COUNTER
WE
CAS
9
*EARLY WRITE
DETECTION CIRCUIT
COLUMN-
ADDRESS
BUFFER(9)
ROW-
ADDRESS
BUFFERS (9)
512
OE
DQ1
DQ2
DQ3
DQ4
4
4
4
4
512
512
512
C
S
R
D
R
(
COLUMN
DECODER
DATA-OUT
BUFFER
DATA-IN
BUFFER
512
SENSE AMPLIFIERS
I/O GATING
512 x 512 x 4
MEMORY
ARRAY
*NOTE:
1. If
W
/
E goes LOW prior to
/
C
/
A
/
S going LOW, EW detection circuit output is a HIGH (EARLY WRITE).
2. If
/
C
/
A
/
S goes LOW prior to
W
/
E going LOW, EW detection circuit output is a LOW (LATE WRITE).
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