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256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65
–
Rev. E; Pub. 3/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
INITIALIZE AND LOAD MODE REGISTER
2
*CAS latency indicated in parentheses.
NOTE:
1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock HIGH time, all commands applied are NOP, with CKE a
“
Don
’
t Care.
”
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at
t
P + 1.
-7E
-75
SYMBOL*
t
CKS
t
CMH
t
CMS
t
MRD
3
t
RFC
t
RP
MIN
1.5
0.8
1.5
2
66
15
MAX
MIN
1.5
0.8
1.5
2
66
20
MAX
UNITS
ns
ns
ns
t
CK
ns
ns
TIMING PARAMETERS
-7E
-75
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CKH
MIN
0.8
1.5
2.5
2.5
7
7.5
0.8
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
0.8
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
tCH
tCL
tCK
CKE
CK
COMMAND
DQ
BA0, BA1
BANK
tRFC
tMRD
tRFC
AUTO REFRESH
AUTO REFRESH
Program Mode Register
1, 3, 4
tCMH
tCMS
Precharge
all banks
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
tRP
(
)
(
)
(
)
(
)
tCKS
Power-up:
V
DD
and
CLK stable
T = 100μs
MIN
PRECHARGE
NOP
RAUTO
NOP
LREGISTER
ACTIVE
NOP
NOP
NOP
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
RAUTO
ALL
BANKS
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
High-Z
tCKH
(
)
(
)
(
)
(
)
DQM/
DQML, DQMU
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
()()
()()
()()
()()
()()
NOP
(
)
(
)
(
)
(
)
A0-A9, A11, A12
ROW
tAH
5
tAS
CODE
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
A10
ROW
tAH
tAS
CODE
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
ALL BANKS
SINGLE BANK
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DON
’
T CARE
UNDEFINED
T0
T1
Tn + 1
To + 1
Tp + 1
Tp + 2
Tp + 3