- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384755 > MT46V64M8TG-8L (Micron Technology, Inc.) DOUBLE DATA RATE DDR SDRAM PDF資料下載
參數(shù)資料
| 型號： | MT46V64M8TG-8L |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 22/68頁 |
| 文件大?。?/td> | 2555K |
| 代理商： | MT46V64M8TG-8L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
22
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
–
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
Data from any READ burst may be truncated with a
BURST TERMINATE command, as shown in Figure 11.
The BURST TERMINATE latency is equal to the READ
(CAS) latency, i.e., the BURST TERMINATE command
should be issued
x
cycles after the READ command,
where
x
equals the number of desired data element
pairs (pairs are required by the 2
n
-prefetch architec-
ture).
Data from any READ burst must be completed or
truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TER-
MINATE command must be used, as shown in Figure
12. The
t
DQSS (MIN) case is shown; the
t
DQSS (MAX)
case has a longer bus idle time. (
t
DQSS [MIN] and
t
DQSS
[MAX] are defined in the section on WRITEs.)
A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank provided
that auto precharge was not activated. The
PRECHARGE command should be issued
x
cycles after
the READ command, where
x
equals the number of
desired data element pairs (pairs are required by the
2
n
-prefetch architecture). This is shown in Figure 13.
Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until
t
RP
is met. Note that part of the row precharge time is hid-
den during the access of the last data elements.
READs (continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT48LC16M8A2 | SYNCHRONOUS DRAM |
| MT48LC2M32B2 | SYNCHRONOUS DRAM |
| MT48LC32M8A2 | SYNCHRONOUS DRAM |
| MT48LC16M16A2 | SYNCHRONOUS DRAM |
| MT48LC64M4A2 | SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V8M16 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。