
6
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
RESERVED NC PINS
1
TQFP PIN NUMBERS
37
44
SYMBOL
A11
A12
TYPE
I
I
DESCRIPTION
Address input for 128Mb and 256Mb devices.
Address input for 256Mb devices. Not Finalized
52
NC (MCL)
No Connect: Not internally connected. Must Connect LOW (for
compatibility with SGRAM devices).
94
DQS
I/O
Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data.
No Connect: These pins should be left unconnected.
37-44
87-90
91
93
NC
–
DNU
RFU
V
DD
Q
–
Do Not Use: Must float to minimize noise.
Reserved for Future Use
Supply DQ Power Supply: Isolated on the die for improved noise
immunity.
Supply DQ Ground. Isolated on the die for improved noise immunity.
2, 8, 14, 22, 59, 67, 73,
79, 86, 95
5, 11, 19, 62, 70, 76,
82, 92, 99
15, 35, 65, 96
16, 46, 66, 85
58
V
SS
Q
V
DD
V
SS
V
REF
Supply
Supply Ground.
Supply SSTL_2 reference voltage.
Power Supply
PIN DESCRIPTIONS (continued)
TQFP PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
NOTE:
1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins
deemed to be of importance.