參數(shù)資料
型號(hào)： MT46V2M32V1
廠商： Micron Technology, Inc.
英文描述： DOUBLE DATA RATE DDR SDRAM
中文描述： 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁(yè)數(shù)： 49/65頁(yè)
文件大?。?/td> 2360K
代理商： MT46V2M32V1
49
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
NOTES (continued)
33. The clock is allowed up to ±175ps of clock to clock
jitter with a ±80ps cumulative jitter. Each AC
timing parameter is also allowed to vary by the
same amount.
34.
t
HP (MIN) is the lesser of
t
CL minimum and
t
CH
minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.
35. READs and WRITEs with autoprecharge are not
allowed to be issued until
t
RAS (MIN) can be
satisfied prior to the internal precharge com-
mand being issued.
36. Impedance match output drive curves:
a)The full variation in driver pull-down current
from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figures A
and B.
b)The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figures A and B.
c) The full variation in driver pull-up current from
minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figures C and D.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figures C and D.
e)The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
will not exceed 1.7, for device drain-to-source
voltages from 0 to V
DD
Q/2.
f) The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±30%, for device drain-to-source voltages from
0 to V
DD
Q/2.
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