
54
64Mb: x32 DDR SDRAM
2M32DDR-07.p65
–
Rev. 12/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32
DDR SDRAM
Figure 30
Data Input Timing
Figure 29
Data Output Timing
–
t
AC and
t
DQSCK
CK
CK#
DQS
T0
7
T1
T2
T3
T4
T5
T2n
T3n
T4n
T5n
T6
NOTE:
1.tDQSCK is the DQS output window relative to CK and is the
“
long term
”
component of DQS skew.
2.
DQs transitioning after DQS transition define tDQSQ window.
3. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC.
4.tAC is the DQ output window relative to CK, and is the
“
long term
”
component of DQ skew.
5.tLZ(
MIN
), tAC(
MIN
) and tHZ(
MIN
) are the first valid signal transition.
6.tLZ(
MAX
), tAC(
MAX
) and tHZ(
MAX
) are the latest valid signal transition.
7. READ command with CL = 2 issued at T0.
tRPST
tLZ(MAX)
tLZ(MIN)
tDQSCK
1
(MAX)
tDQSCK
1
(MIN)
tDQSCK
1
(MAX)
tDQSCK
1
(MIN)
tHZ(MAX)
tHZ(MIN)
tRPRE
DQ (Last data valid)
DQ (First data valid)
All DQs collectively
3
tAC
4
(
MIN
)
tAC
4
(
MAX
)
tLZ(MAX
)
tLZ
(
MIN
)
tHZ
(
MAX
)
tHZ
(
MIN
)
T2
T2
T2n
T3n
T4n
T5n
T2n
T2n
T3n
T3n
T4n
T4n
T5n
T5n
T3
T4
T4
T5
T5
T2
T3
T4
T5
T3
DQS
tDQSS
tDQSHtWPST
tDH
tDS
tDQSL
tDSS2
tDSH1
tDSH1
tDSS2
DM
DQ
CK
CK#
T0
3
T1
T1n
T2
T2n
T3
DI
b
NOTE:
1.tDSH(MIN) generally occurs during tDQSS(MIN).
2.tDSS(MIN) generally occurs during tDQSS(MAX).
3. WRITE command issued at T0.
DON
’
T CARE
TRANSITIONING DATA
t
WPRE
t
WPRES