
Chapter 5 Clock Generation Circuit (2CLK)
5.1 Overview .......................................................................................................... 5-1
5.2 Layout of Clock Generation Circuit .................................................................. 5-1
5.3 Operation of Clock Generation Circuit ............................................................. 5-2
5.4 Frequency Control Register (FCON) ............................................................... 5-2
5.5 System Clock Switch Timing ............................................................................ 5-3
Chapter 6 Time Base Counter (TBC)
6.1 Overview .......................................................................................................... 6-1
6.2 Layout of Time Base Counter .......................................................................... 6-1
6.3 Operation of Time Base Counter ..................................................................... 6-2
6.4 Time Base Counter Register (TBCR) .............................................................. 6-2
Chapter 7 Ports (P0, P1, P2, P3 and P4)
7.1 Overview .......................................................................................................... 7-1
7.2 Port 0 and Port 1 (P0.0 to P0.3 and P1.0 to P1.3) ........................................... 7-2
7.2.1 Layout of Port 0 and Port 1 ................................................................... 7-2
7.2.2 Registers Related to Port 0 and Port 1 ................................................. 7-4
7.2.3 External Interrupt Generation Timing of Port 0 ..................................... 7-7
7.3 Port 2, Port 3 and Port 4 (P2.0 to P2.3, P3.0 to P3.3 and P4.0 to P4.3) ......... 7-9
7.3.1 Layout of Port 2, Port 3 and Port 4 ....................................................... 7-9
7.3.2 Registers Related to Port 2, Port 3 and Port 4 ..................................... 7-11
7.3.3 External Interrupt Generation Timing of Port 2, Port 3 and Port 4 ........ 7-27
Chapter 8 Serial Port (SIOP)
8.1 Overview .......................................................................................................... 8-1
8.2 Layout of Serial Port ........................................................................................ 8-2
8.3 Operation of Serial Port ................................................................................... 8-3
8.4 Registers Related to Serial Port ....................................................................... 8-5
Chapter 9 Buzzer Driver (BD)
9.1 Overview .......................................................................................................... 9-1
9.2 Layout of Buzzer Driver ................................................................................... 9-1
9.3 Operation of Buzzer Driver .............................................................................. 9-1
9.4 Registers Related to Buzzer Driver .................................................................. 9-3
9.5 BD Output Waveform and External Circuit ...................................................... 9-5
Chapter 10 Capture Circuit (CAPR)
10.1 Overview .......................................................................................................... 10-1
10.2 Layout of Capture Circuit ................................................................................. 10-1
10.3 Operation of Capture Circuit ............................................................................ 10-2
10.4 Registers Related to Capture Circuit ............................................................... 10-3
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