參數(shù)資料
型號(hào)： MSM6262-04GS-BK
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 顯示控制器
英文描述： 48 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 37/53頁(yè)
文件大小： 602K
代理商： MSM6262-04GS-BK
Semiconductor
MSM6262-04
42/53
FEDL6262-04-03
B1F (Busy 1 flag)
When B1F = "H", MSM6262-04 is engaged in internal operation and next instruction is not
accepted until when B1F becomes "L". So, subsequent instruction has to be input after B1F
is confirmed at "L". During B1F = "H", DB5 to DB0 are undefined.
B2F (Busy 2 flag)
B2F indicates that MSM6262-04 is engaged in its internal operation and it also indicates
that the display starting line is under being revised.
Instruction contents of B1F and B2F are the same except when setting the starting line of
display.
B2F = "H" indicates that MSM6262-04 is engaged in its internal operation. B2F = "L"
indicates that MAM6262-04 is ready for accepting new instruction.
Even when B2F = "H", new instruction can be accepted if B1F = "L". However, if the
starting line of display is revised under this condition, the previous set data about
starting line of display becomes invalid and the newly input data about starting line
becomes valid.
Instruction
code
A1
A0
DB7
DB6
DB5
DB3
DB2
DB1
DB0
DB4
LH
D06
D05
D04
D03
D02
D01
D00
D07
Instruction
code
A1
A0
DB7
DB6
DB5
DB3
DB2
DB1
DB0
DB4
HL
A06
A05
A04
A03
A02
A01
A00
A07
Instruction
code
A1
A0
DB7
DB6
DB5
DB3
DB2
DB1
DB0
DB4
H
B1F
CG/
B2F
DD
I/D
S
A/O
D
UD
(12) CG RAM and DD RAM data read
This instruction reads the 8-bit data (DO7 to DO0) from either CG RAM or DD RAM.
Determination of CG RAM or DD RAM is made by the previously set CG RAM or DD
RAM address set.
The CG RAM address set instruction or DD RAM address set instruction has to be input
just before executing this read instruction. If it is not input, the first output of the data
becomes invalid. When this read instruction is performed continuously, normal data is
output from the 2nd data onward.
In the case of DD RAM data read, normal data is output from the first data even if the
address set is not input, provided that cursor is moved by the cursor shift instruction.
After reading the data, the address is incremented or decremented by 1 by the entry
mode.
The shift of the display, however, is not performed.
(13) Address counter read
This instruction reads the 8-bit data (AO7 to AO0) . Address counter is determined by the
previously set address set because it is used for both CG RAM and DD RAM.
(14) Busy flag read
相關(guān)PDF資料
PDF描述
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