參數(shù)資料
型號(hào): MSM6262-04GS-BK
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 顯示控制器
英文描述: 48 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80
封裝: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù): 13/53頁(yè)
文件大?。?/td> 602K
代理商: MSM6262-04GS-BK
Semiconductor
MSM6262-04
20/53
FEDL6262-04-03
4. Timing Generator Circuit
This circuit generates the timing signal for the internal operation by CPU's instruction as well
as to operate the internal circuit of DD RAM, CG RAM, CG ROM and so forth. It also generates
the transfer signal to the SEGMENT driver (MSM5839C or MSM5259).
The internal operation accessed by the CPU and internal operation for LCD display is
independent.
So, a manipulation such as writing data from CPU to DD RAM will not have an influence such
as display flickering upon any part other than the display part to which the data is written.
5. Display Data RAM (DD RAM)
DD RAM is used to store the 8-bit character code (refer to Table 1) and 1-bit under-line data.
The address of DD RAM corresponds to the display position on the LCD. The correspondence
is described below.
DD RAM address (set to ADC) is described as hexadecimal.
(1) Relation between DD RAM and display position in 2-line display mode
1
2
3
4
5
– – –
79
80
– – –
00
80
01
81
02
82
03
83
04
84
4E
CE
4F
CF
1st line
2nd line
Digit
Display position
DD RAM address
(hexadecimal)
1st line
2nd line
00
80
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15 16
01
81
02
82
03
83
04
84
05
85
06
86
07
87
08
88
09
89
0A
8A
0B
8B
0C
8C
0D
8D
0E
8E
0F
8F
Digit
MSM5839C (2)
MSM5259 (2) }
MSM5839C (1)
MSM5259 (1)
{ or
Note: The address of the last digit of the first line and the first digit of the second line
does not have any continuity.
DB7
DB6 DB5
DB4
DB3 DB2
DB1 DB0
MSB
LSB
Hexadecimal
Example: When DD RAM address is 3A
3A
LL
LH
H
L
H
ADC
(2) When 2 pieces of MSM5389C(or MSM5259) are connected to MSM6262-04, 32
characters can be displayed from the first digit to yhe 16th degit.
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