參數(shù)資料
型號： MSC8252TVT1000B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783
文件頁數(shù)： 24/68頁
文件大?。?/td> 912K
代理商： MSC8252TVT1000B
MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 5
Electrical Characteristics
Freescale Semiconductor
30
2.5.2.3
SerDes Transmitter and Receiver Reference Circuits
Figure 6 shows the reference circuits for SerDes data lane transmitter and receiver.
2.5.3
DC-Level Requirements for SerDes Interfaces
The following subsections define the DC-level requirements for the SerDes reference clocks, the PCI Express data lines, the
Serial RapidIO data lines, and the SGMII data lines.
2.5.3.1
DC-Level Requirements for SerDes Reference Clocks
The DC-level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For an external DC-coupled connection, the maximum average current requirements sets the requirement for
average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 7 shows the SerDes reference
clock input requirement for DC-coupled connection scheme.
Figure 6. SerDes Transmitter and Receiver Reference Circuits
Figure 7. Differential Reference Clock Input DC Requirements (External DC-Coupled)
50
Ω
50
Ω
50
Ω
50
Ω
Transmitter
Receiver
SR[1–2]_TXm
SR[1–2]_RXm
SR[1–2]_TXm
SR[1–2]_RXm
Note: The [1–2] indicates the specific SerDes Interface (1 or 2) and the m indicates the
specific channel within that interface (0,1,2,3). Actual signals are assigned by the
HRCW assignments at reset (see Chapter 5, Reset in the reference manual for details)
SR[1–2]_REF_CLK
Vmax < 800 mV
Vmin > 0V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
相關PDF資料
PDF描述
MSC8252SVT1000B 0-BIT, OTHER DSP, PBGA783
MSD1010LT3 100 mA, 15 V, PNP, Si, SMALL SIGNAL TRANSISTOR
MSD1010LT1 100 mA, 15 V, PNP, Si, SMALL SIGNAL TRANSISTOR
MMBT1010LT3 100 mA, 15 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-236AB
MSD1328-RT3 500 mA, 20 V, NPN, Si, SMALL SIGNAL TRANSISTOR
相關代理商/技術參數(shù)
參數(shù)描述
MSC8254 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad-Core Digital Signal Processor
MSC8254_11 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad-Core Digital Signal Processor
MSC8254SVT1000B 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSPStarcore4-core R2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MSC8254SVT800B 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSPStarcore 4-core RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MSC8254TVT1000B 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSPStarcore 4-core RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*