參數(shù)資料
型號(hào)： MSC8113TVT4800V
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 13/44頁(yè)
文件大?。?/td> 0K
描述： DSP TRI-CORE 431-FCPBGA
標(biāo)準(zhǔn)包裝： 60
系列： StarCore
類型： SC140 內(nèi)核
接口： 以太網(wǎng)，I²C，TDM，UART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.436MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.10V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 431-BFBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 431-FCPBGA（20x20）
包裝： 托盤
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Electrical Characteristics
Freescale Semiconductor
20
2.5.4.2
Reset Configuration
The MSC8113 has two mechanisms for writing the reset configuration:
Through the direct slave interface (DSI)
Through the system bus. When the reset configuration is written through the system bus, the MSC8113 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is
written, a default configuration word is applied.
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset
Configuration Mode and boot and operating conditions:
RSTCONF
CNFGS
DSISYNC
DSI64
CHIP_ID[0–3]
BM[0–2]
SWTE
MODCK[1–2]
2.5.4.3
Reset Timing Tables
Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or
through the system bus.
Table 12. Timing for a Reset Configuration Write through the DSI or System Bus
No.
Characteristics
Expression
Min
Max
Unit
1
Required external PORESET duration minimum
CLKIN = 20 MHz
CLKIN = 100 MHz (300 MHz core)
CLKIN = 133 MHz (400 MHz core)
16/CLKIN
800
160
120
—
ns
2
Delay from deassertion of external PORESET to deassertion of internal
PORESET
CLKIN = 20 MHz to 133 MHz
1024/CLKIN
6.17
51.2
s
3
Delay from de-assertion of internal PORESET to SPLL lock
CLKIN = 20 MHz (RDF = 1)
CLKIN = 100 MHz (RDF = 1) (300 MHz core)
CLKIN = 133 MHz (RDF = 2) (400 MHz core)
6400/(CLKIN/RDF)
(PLL reference
clock-division factor)
320
64
96
320
64
96
s
5
Delay from SPLL to HRESET deassertion
REFCLK = 40 MHz to 133 MHz
512/REFCLK
3.08
12.8
s
6
Delay from SPLL lock to SRESET deassertion
REFCLK = 40 MHz to 133 MHz
515/REFCLK
3.10
12.88
s
7
Setup time from assertion of
RSTCONF, CNFGS, DSISYNC, DSI64,
CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of
PORESET
3—
ns
8
Hold time from deassertion of PORESET to deassertion of
RSTCONF,
CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and
MODCK[1–2]
5—
ns
Note:
Timings are not tested, but are guaranteed by design.
相關(guān)PDF資料
PDF描述
MSC8122MP8000 DSP 16BIT 500MHZ MULTI 431FCPBGA
MSC8144VT800A IC DSP QUAD 800MHZ 783FCBGA
MSC8154SVT1000B IC PROCESSOR QUAD DGTL 783FCPBGA
MSC8156TVT1000B IC PROCESSOR QUAD DGTL 783FCPBGA
MSC8251TVT1000B IC DSP SINGLE 1GHZ 783FCPBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8113TVT4800V 制造商:Freescale Semiconductor 功能描述:Tri-Core Digital Signal Processor
MSC8113-V1 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Tri-Core Digital Signal
MSC8120 制造商:FOSSE 功能描述:MAINTENANCE ABSORB SOCK
MSC8122 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Digital Signal Processor
MSC8122_07 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Digital Signal Processor
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*