參數(shù)資料
型號: MSC8101VT1250F
廠商: Freescale Semiconductor
文件頁數(shù): 56/104頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 250MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝: 90
系列: StarCore
類型: SC140 內(nèi)核
接口: 通信處理器模塊(CPM)
時鐘速率: 250MHz
非易失內(nèi)存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.60V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 332-BFBGA,F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝: 332-FCBGA(17x17)
包裝: 托盤
AC Timings
MSC8101 Technical Data, Rev. 19
Freescale Semiconductor
2-15
35c
BG delay from the 50% level of the DLLIN rising edge
1.0
4.0
5.5
ns
35d
TS delay from the 50% level of the DLLIN rising edge
1.0
3.5
5.0
ns
36
Delay from the 50% level of the DLLIN rising edge for all other signals
1.0
4.5
6.0
ns
Notes:
1.
The maximum bus frequency depends on the mode:
In 60x-compatible mode connected to another MSC8101 device, the frequency is determined by adding the input and output
longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. In multi-master mode when
connected to another MSC8101 device, the frequency is determined by adding the input and output longest timing values,
which results in a frequency of 75 MHz for 30 pF output capacitance.
Certain bus modes, such as non-extra cycle (EXDD = 1), non-pipelined, and ECC/Parity modes, result in slower bus
frequencies.
In single-master mode, the frequency depends on the timing of the devices connected to the MSC8101.
2.
Output specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are
measured at the pin.
Table 2-17.
AC Timing for SIU Outputs
No.
Characteristic
Min.
Maximum2
Units
30 pF
50 pF
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