參數(shù)資料
型號(hào)： MSC8101VT1250F
廠(chǎng)商： Freescale Semiconductor
文件頁(yè)數(shù)： 20/104頁(yè)
文件大小： 0K
描述： IC DSP 16BIT 250MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類(lèi)型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時(shí)鐘速率： 250MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤(pán)
MSC8101 Technical Data, Rev. 19
1-18
Freescale Semiconductor
Signals/Connections
PA22
FCC1: TXD3
UTOPIA
Output
FCC1: UTOPIA Transmit Data Bit 3
The MSC8101 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 3 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
PA21
FCC1: TXD4
UTOPIA
FCC1: TXD3
MII and HDLC nibble
Output
FCC1: UTOPIA Transmit Data Bit 4
The MSC8101 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 4 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 3
TXD[3–0] supports MII and HDLC nibble modes in FCC1. TXD3 is the
most significant bit.
PA20
FCC1: TXD5
UTOPIA
FCC1: TXD2
MII and HDLC nibble
Output
FCC1: UTOPIA Transmit Data Bit 5
The MSC8101 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 5 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 2
TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. This is
bit 2 of the transmit data. TXD3 is the most significant bit.
PA19
FCC1: TXD6
UTOPIA
FCC1: TXD1
MII and HDLC nibble
Output
FCC1: UTOPIA Transmit Data Bit 6
The MSC8101MSC8101 outputs ATM cell octets (UTOPIA interface
data) on TXD[0–7]. This is bit 6 of the transmit data. TXD7 is the most
significant bit. When no ATM data is available, idle cells are inserted. A
cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 1
TXD[3–0] is supported by MII and HDLC transparent nibble modes in
FCC1. This is bit 1 of the transmit data. TXD3 is the most significant bit.
PA18
FCC1: TXD7
UTOPIA
FCC1: TXD0
MII and HDLC nibble
FCC1: TXD
HDLC serial and transparent
Output
FCC1: UTOPIA Transmit Data Bit 7.
The MSC8101 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. TXD7 is the most significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 0
TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. TXD0
is the least significant bit.
FCC1: HDLC Serial and Transparent Transmit Data Bit
This is the single transmit data bit in supported by HDLC serial and
transparent modes.
Table 1-7.
Port A Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated Signal
Protocol
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