參數(shù)資料
型號(hào)： MSC7116VF1000
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
中文描述： 低成本16位數(shù)字信號(hào)處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC
文件頁(yè)數(shù)： 45/56頁(yè)
文件大小： 719K
代理商： MSC7116VF1000
Hardware Design Considerations
MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11
Freescale Semiconductor
45
3.3.2
Peripheral Power
Peripherals include the DDR memory controller, Ethernet controller, DMA controller, HDI16, TDM, UART, timers, GPIOs,
and the I
2
C module. Basic power consumption by each module is assumed to be the same and is computed by using the
following equation which assumes an effective load of 20 pF, core voltage swing of 1.2 V, and a switching frequency of 133
MHz. This yields:
P
PERIPHERAL
= 20 pF
×
(1.2 V)
2
×
133 MHz
×
10
–3
= 3.83 mW per peripheral
Eqn. 6
Multiply this value by the number of peripherals used in the application to compute the total peripheral power consumption.
3.3.3
External Memory Power
Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage,
termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7116
device, the 2.5 V power source provides the power for the termination, which is a static value of 16 mA per signal driven high.
The dynamic power is computed, however, using a differential voltage swing of ±0.200 V, yielding a peak-to-peak swing of 0.4
V. The equations for computing the DDR power are:
P
DDRIO
= P
STATIC
+ P
DYNAMIC
Eqn. 7
P
STATIC
= (unused pins
×
% driven high)
×
16 mA
×
2.5 V
Eqn. 8
P
DYNAMIC
= (pin activity value)
×
20 pF
×
(0.4 V)
2
×
266 MHz
×
10
–3
mW
Eqn. 9
pin activity value = (active data lines
×
% activity
×
% data switching) + (active address lines
×
% activity)
Eqn. 10
As an example, assume the following:
unused pins = 16 (DDR uses 16-pin mode)
% driven high = 50%
active data lines = 16
% activity = 60%
% data switching = 50%
active address lines = 3
In this example, the DDR memory power consumption is:
P
DDRIO
= ((16
×
0.5)
×
16
×
2.5) + (((16
×
0.6
×
0.5) + (3
×
0.6))
×
20
×
(0.4)
2
×
266
×
10
–3
) = 326.3 mW
Eqn. 11
3.3.4
External I/O Power
The estimation of the I/O power is similar to the computation of the peripheral power estimates. The power consumption per
signal line is computed assuming a maximum load of 20 pF, a voltage swing of 3.3 V, and a switching frequency of 33 MHz,
which yields:
P
IO
= 20 pF
×
(3.3 V)
2
×
33 MHz
×
10
–3
= 7.19 mW per I/O line
Eqn. 12
Multiply this number by the number of I/O signal lines used in the application design to compute the total I/O power.
Note:
The signal loading depends on the board routing. For systems using a single DDR device, the load could be as low as
7 pF.
3.3.5
Leakage Power
The leakage power is for all power supplies combined at a specific temperature. The value is temperature dependent. The
observed leakage value at room temperature is 64 mW.
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