參數(shù)資料
型號: MSC7116VF1000
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
中文描述: 低成本16位數(shù)字信號處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC
文件頁數(shù): 38/56頁
文件大?。?/td> 719K
代理商: MSC7116VF1000
MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11
Freescale Semiconductor
38
2.5.11
Event Timing
Figure 24
shows the signal behavior of the EVNT pins.
2.5.12
GPIO Timing
Figure 25
shows the signal behavior of the
GPI/GPO
pins.
Table 29. EVNT Signal Timing
Number
Characteristics
Type
Min
67
68
EVNT as input
EVNT as output
Refer to
Table 27
for a definition of the APBCLK period.
Direction of the EVNT signal is configured through the GPIO and Event port registers.
Refer to the signal chapter in the
MSC711x Reference Manual
for details on EVNT pin functionality.
Asynchronous
Synchronous to core clock
1.5
×
APBCLK periods
1 APBCLK period
Notes:
1.
2.
3.
Figure 24. EVNT Pin Timing
Table 30. GPIO Signal Timing
1,2,3
Number
Characteristics
Type
Min
601
602
603
604
GPI
4.5
GPO
5
Port A edge-sensitive interrupt
Port A level-sensitive interrupt
Refer to
Table 27
for a definition of the APBCLK period.
Direction of the GPIO signal is configured through the GPIO port registers.
Refer to
Section 1.5
for details on GPIO pin functionality.
GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data
into a register when the GPADR is read. The specification is not tested due to the asynchronous nature of the input and
dependence on the state of the DSP core. It is guaranteed by design.
The output signals cannot toggle faster than 75 MHz.
Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is
acknowledged.
Asynchronous
Synchronous to core clock
Asynchronous
Asynchronous
1.5
×
APBCLK periods
1 APBCLK period
1.5
×
APBCLK periods
3
×
APBCLK periods
6
Notes:
1.
2.
3.
4.
5.
6.
Figure 25. GPI/GPO Pin Timing
EVNT in
67
EVNT out
68
GPI
601
GPO
602
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