參數(shù)資料
型號： MSC1210Y3PAGTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁數(shù)： 6/94頁
文件大?。?/td> 913K
代理商： MSC1210Y3PAGTG4
MSC1210
SBAS203J MARCH 2002 REVISED JANUARY 2008
www.ti.com
14
PIN DESCRIPTIONS (continued)
PIN #
DESCRIPTION
NAME
44
PSEN,
OSCCLK,
MODCLK
Program store enable. Connected to optional external memory as a chip enable. PSEN provides an active low pulse.
In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode.
PSEN is held HIGH for parallel programming mode and LOW for serial programming. This pin can also be selected
(when not using external memory) to output the oscillator clock, modulator clock, HIGH, or LOW. Care should be
taken so that loading on this pin does not inadvertently cause the device to enter programming mode.
ALE
PSEN
Program Mode Selection(1)
NC or DVDD
Normal operation (User Application mode)
0
NC or DVDD
Parallel programming
NC or DVDD
0
Serial programming
0
Reserved
45
ALE
Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted
at a constant rate of 1/4 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is
skipped during each access to external data memory. In programming mode, ALE is used as an input along with PSEN to
define serial or parallel programming mode. ALE is held HIGH for serial programming mode and LOW for parallel
programming. This pin can also be selected (when not using external memory) to output HIGH or LOW. Care should be
taken so that loading on this pin does not inadvertently cause the device to enter programming mode.
48
EA
External Access Enable: EA must be externally held LOW at the end of RESET to enable the device to fetch code
from external program memory locations starting with 0000h. No internal pull-up on this pin.
46, 47, 4954
P0.0P0.7
Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below. Refer to P1DDR, SFR AEhAFh.
46, 47, 4954
P0.0P0.7
PORT 0.x
Alternate Name
Alternate Use
P0.0
AD0
Address/Data bit 0
P0.1
AD1
Address/Data bit 1
P0.2
AD2
Address/Data bit 2
P0.3
AD3
Address/Data bit 3
P0.4
AD4
Address/Data bit 4
P0.5
AD5
Address/Data bit 5
P0.6
AD6
Address/Data bit 6
P0.7
AD7
Address/Data bit 7
55, 56, 5964
P1.0P1.7
Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below. Refer to P1DDR, SFR AEhAFh.
55, 56, 5964
P1.0P1.7
PORT 0.x
Alternate Name(s)
Alternate Use
P1.0
T2
T2 input
P1.1
T2EX
T2 external input
P1.2
RxD1
Serial port input
P1.3
TxD1
Serial port output
P1.4
INT2/SS
External Interrupt / Slave Select
P1.5
INT3/MOSI
External Interrupt / Master OutSlave In
P1.6
INT4/MISO
External Interrupt / Master InSlave Out
P1.7
INT5/SCK
External Interrupt / Serial Clock
(1) The program mode is changed during the falling edge of the reset signal.
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MSC1210Y4PAGTG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Prec ADC w/ 8051 Mcntrl & Flash RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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