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參數(shù)資料
| 型號： | MSC1200Y3PFBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 72/93頁 |
| 文件大小： | 1093K |
| 代理商： | MSC1200Y3PFBT |
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MSC1200
MSC1201
MSC1202
SBAS317E APRIL 2004 REVISED MAY 2006
www.ti.com
74
Summation 0 (SUMR0)
7
6
5
4
3
2
1
0
Reset Value
SFR E2h
LSB
00h
SUMR0
Summation 0. This is the least significant byte of the 32-bit summation register, or bits 0 to 7.
bits 70
Write: Will cause values in SUMR30 to be added to the summation register.
Read: Will clear the Summation Interrupt.
Summation 1 (SUMR1)
7
6
5
4
3
2
1
0
Reset Value
SFR E3h
00h
SUMR1
Summation 1. This is the most significant byte of the lowest 16 bits of the summation register, or bits 815.
bits 70
Summation 2 (SUMR2)
7
6
5
4
3
2
1
0
Reset Value
SFR E4h
00h
SUMR2
Summation 2. This is the most significant byte of the lowest 24 bits of the summation register, or bits 1623.
bits 70
Summation 3 (SUMR3)
7
6
5
4
3
2
1
0
Reset Value
SFR E5h
MSB
00h
SUMR3
Summation 3. This is the most significant byte of the 32-bit summation register, or bits 2431.
bits 70
Offset DAC (ODAC)
7
6
5
4
3
2
1
0
Reset Value
SFR E6h
00h
ODAC
Offset DAC. This register will shift the input by up to half of the ADC full-scale input range. The Offset DAC
bits 70
value is summed into the ADC prior to conversion. Writing 00h or 80h to ODAC turns off the Offset DAC. The offset
DAC should be cleared prior to calibration, since the offset DAC analog output is applied directly to the ADC input.
bit 7
Offset DAC Sign Bit.
0 = Positive
1 = Negative
bit 60
Offset
+
*V
REF
2
@ PGA @
ODAC [ 6 : 0]
127
@ (*1)
bit7
NOTE: ODAC cannot be used to offset the analog inputs so that the buffer can be used for signals within 50mV of AGND.
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